Senior DFT Engineer

Nvidia

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Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $136,000–$218,500 / yr
Employment: Full-time
Posted: 18 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $191k

This role $177k

$124k most similar roles pay here $247k

This role pays less than 58% of similar roles. Most pay $165,846–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $191k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1391 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1116 roles with salary data.

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At a glance

TL;DR · Senior DFT Engineer

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As a Senior DFT Engineer, you will join a world-class team to lead silicon test innovation for next-generation platforms. You will design and roll out advanced test methodologies, owning the implementation of test access mechanisms, IO BIST, memory BIST, and scan compression. Your daily work involves collaborating with VLSI and Product Engineering groups to develop innovative DFT approaches while leading end-to-end planning for chip bring-up from pre-silicon through production deployment. You will also standardize workflows, create reusable playbooks, and mentor junior engineers on complex build trade-offs. The role requires expertise in scan test plans, fault modeling, ATPG, and fault simulation using vendor tools. Essential skills include programming, scripting, and silicon debug experience with an understanding of pattern formats and failure processing to solve complex challenges within multi-million gate builds.

Skills

DFT Scan Compression BIST ATPG Fault Modeling Silicon Bring-up VLSI Scripting Oscilloscopes Logic Analyzers SoC Test Program Development Verification Validation RAS InSystem Test

What you'll do

Design and roll out advanced test methodologies on next-generation silicon platforms.
Implement test access mechanisms, IO BIST, memory BIST, and scan compression.
Develop innovative DFT approaches in collaboration with VLSI and Product Engineering groups.
Lead end-to-end planning and execution of chip bring-up from pre-silicon to production.
Create and standardize methodologies, processes, and reusable playbooks for silicon bring-up.
Verify and validate test patterns and logic on complex multi-million gate builds.
Perform silicon debug and develop test programs using various pattern formats.
Mentor junior engineers on technical trade-offs to achieve high quality and efficiency.

What we're looking for

BSEE with 5+ years of experience, MSEE with 3+ years, or a PhD in DFT or related domains.
Expertise in scan test plans, BIST (memory and IO), fault modeling, ATPG, and fault simulation.
Experience in silicon debug and bring-up including pattern formats, failure processing, and test program development.
Strong programming and scripting skills.
Excellent written and oral communication skills.
Deep understanding of DFT architecture (preferred).
Direct bring-up experience on GPU/SoC (preferred).
Hands-on validation skills with oscilloscopes, logic analyzers, and lab debugging (preferred).

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