Senior DFT Engineer

Nvidia

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAAustin, TX
Salary: $168,000–$264,500 / yr
Posted: 4 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $185k

This role $216k

$129k most similar roles pay here $279k

This role pays more than 83% of similar roles. Most pay $155,900–$213,731 — the shaded band above. At the midpoint, this role pays about $216k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 929 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 915 roles with salary data.

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At a glance

TL;DR · Senior DFT Engineer

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Senior DFT Engineer joins the DFX team to manage the Scan Test Lifecycle for advanced silicon including 2.5D/3D AI data center platforms, Gaming and Enterprise GPUs, and complex SOCs for autonomous machines and robotics. This role involves designing and prototyping test architectures for reticle sized, multi-chiplet products from RTL through verification to post-silicon ATE bring-up. Key responsibilities include developing industry-leading test methodologies, collaborating with EDA vendors to shape tool capabilities, and owning the full ATPG lifecycle including coverage analysis and pattern generation. The candidate will utilize industry standard ATPG tools while potentially leveraging programming languages and AI for automation. The role requires deep knowledge of DFT strategies for large-scale designs and involves mentoring junior engineers to navigate complex design trade-offs while ensuring high quality and efficiency across a diverse product portfolio.

Skills

DFT ATPG ATE Scan Test VLSI RTL 2.5D/3D ICs Multi-chiplet Architecture Silicon Testing AI CAD Automated Solutions

What you'll do

Develop and deploy advanced test methodologies for next-generation silicon platforms.
Partner with EDA vendors to shape tool capabilities that meet specific design goals.
Collaborate with internal CAD teams to develop scalable and automated testing solutions.
Co-architect novel DFT strategies alongside VLSI and Product Engineering teams.
Manage the full ATPG lifecycle including verification, coverage analysis, and pattern generation.
Execute ATE bring-up for complex multi-chiplet products and large-scale designs.
Mentor junior engineers on design trade-offs to ensure high quality and efficiency.

What we're looking for

MS/PhD or equivalent experience in Electrical Engineering or a related field.
6+ years of hands-on experience in Design-For-Test (DFT).
Deep knowledge of DFT tools, methodologies, and test strategies for complex, large-scale designs.
Strong experience with industry standard ATPG tools.
Clear, effective written and verbal communication skills.
Experience with 2.5D/3D ICs, multi-chiplet architectures, or reticle-sized designs (preferred).
Background in developing or enhancing EDA tool flows (preferred).
Experience with Silicon testing, Automatic Test Equipment (ATE), programming languages, and AI for automation (preferred).

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