Senior ASIC Verification Engineer

Nvidia

Confirmed live today Low trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Employment: Full-time
Posted: 103 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Similar $192k

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior ASIC Verification Engineer

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The Senior ASIC Verification Engineer joins the ASIC Verification team to verify the design and implementation of leading GPUs. This role involves verifying the ASIC design, architecture, golden models, and micro-architecture using advanced methodologies like UVM. The engineer will define verification scope, develop infrastructure, and verify design correctness while collaborating with architects, designers, and pre- and post-silicon verification teams. Key responsibilities include crafting test bench environments for unit and system-level verification using random stimulus, functional coverage, and assertion-based methodologies. Required skills include expertise in SystemVerilog, C++ with object-oriented programming, and experience with tools like VCS, Debussy, and GDB. Candidates must understand computer architecture, digital build, and processor pipeline verification to solve complex hardware design and implementation problems for consumer graphics and artificial intelligence products.

Skills

SystemVerilog UVM C++ VCS Assertion-Based Verification Random Stimulus Functional Coverage GDB Debussy Computer Architecture Object-Oriented Programming Processor Pipeline Verification

What you'll do

Verify the design and implementation of industry-leading GPUs.
Verify ASIC designs, architectures, golden models, and micro-architectures using UVM or equivalent methodologies.
Define the verification scope and develop the necessary verification infrastructure for specific units.
Verify the correctness of the design through rigorous testing.
Craft test bench environments for both unit-level and system-level verification.
Utilize random stimulus, functional coverage, and assertion-based verification methodologies.
Perform debugging and analysis using tools like VCS, Debussy, and GDB.

What we're looking for

Bachelor’s Degree in EE, CS, or CE, or equivalent experience.
6+ years of relevant experience.
Experience in verification using random stimulus, functional coverage, and assertion-based verification methodologies.
Experience with design and verification tools such as VCS, Debussy, or GDB.
Experience crafting test bench environments for unit- and system-level verification.
Expertise in SystemVerilog or a similar Hardware Verification Language.
C++ programming experience with a strong understanding of object-oriented programming, data structures, and algorithms.
Good working knowledge of computer architecture fundamentals and digital build.
Prior experience with processor pipeline verification (preferred).

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