ASIC Design Verification Engineer

Cisco

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$167,700–$245,200 / yr
Posted
3 days ago
Freshness
Confirmed live 2 days ago
Closes
Oct 9, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $189k
This role $206k
$130k most similar roles pay here $258k

This role pays more than 65% of similar roles. Most pay $162,000–$216,062 — the shaded band above. At the midpoint, this role pays about $206k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 196 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 196 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer

As an ASIC Design Verification Engineer within the Common Hardware Group, you will shape the verification methodology and execution across multiple programs and product lines. You will serve as a technical authority and mentor for verification teams while leading the architecture and implementation of scalable, reusable verification infrastructure. Your daily responsibilities include driving cross-functional initiatives to improve quality and coverage, influencing ASIC architecture for robust verification, and providing leadership during root cause analysis and post-silicon validation. The role requires proficiency in SystemVerilog, UVM, and scripting languages like Python and Perl, along with C/C++ programming. You will apply these skills to solve complex problems in the domain of high-performance hardware platforms, specifically focusing on silicon, optics, and infrastructure for switching, routing, and wireless products within the AI era.

What you'll do

  • Set vision and strategy for ASIC verification methodology across multiple programs and product lines.
  • Serve as the technical authority and mentor to foster excellence within verification teams.
  • Architect and implement scalable, reusable verification infrastructure and methodologies.
  • Drive cross-functional initiatives to improve verification efficiency, quality, and coverage at scale.
  • Influence ASIC architecture and design to ensure robust verification and high-quality silicon.
  • Act as a subject matter expert on industry trends, best practices, and new technologies.
  • Provide technical leadership for root cause analysis during bring-up and post-silicon validation.

What we're looking for

  • Bachelor's degree plus 7 years of experience, Master's plus 4 years, or PhD plus 1 year of related experience.
  • Experience in System Verilog, UVM, and verification methodologies including emulation.
  • Experience architecting verification strategies for complex ASIC programs.
  • Experience leading verification teams or projects.
  • Proficiency in scripting languages such as Python or Perl and C/C++ programming.
  • Expertise in multiple protocols and large-scale SoC architectures.
  • Experience with advanced emulation, prototyping, and formal verification tools at scale.
  • Experience with silicon bring-up and post-silicon debug.

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