Senior ASIC Design Engineer

HP Inc.

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Vancouver, WA
Salary
$116,150–$182,400 / yr
Posted
44 days ago
Freshness
Confirmed live yesterday
Closes
Jan 25, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $194k
This role $149k
$103k most similar roles pay here $243k

This role pays less than 92% of similar roles. Most pay $172,000–$216,250 — the shaded band above. At the midpoint, this role pays about $149k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About HP Inc.

HP Inc. is a global technology company that develops and sells personal computers, printers, and related supplies and services. Its products include laptops, desktops, workstations, and printing solutions for consumers and businesses worldwide.

HP Inc. currently has 104 open roles on FindRole.

Listed pay typically runs $130,700–$205,200 across 90 roles with salary data.

Most-posted roles

View all roles at HP Inc.

At a glance

TL;DR · Senior ASIC Design Engineer

As a Senior ASIC Design Engineer on the R&D digital Application-Specific Integrated Circuit design team, you will develop main controllers containing proprietary intellectual property for printer technology. You will lead functional blocks and subsystems from initial design through silicon verification, including RTL coding, verification, silicon validation, and qualification. Your daily work involves collaborating with internal and external partners to align on specifications, manage ASIC roadmaps, and triage hardware and firmware integration issues. You will also contribute to Inkjet and Laserjet print architecture and prototype designs in FPGA or software models. Required skills include expertise in submicron semiconductor technology, Synopsys and Cadence EDA tools, and proficiency in Verilog, SV, Python, Perl, C, and C++. Experience with Git, Subversion, and potential focus on ARM microprocessors or memory subsystems is highly valued for this role.

What does a ASIC Design Engineer earn?

Median $214000 from 51 postings across 9 companies.

See salary data

What you'll do

  • Lead functional blocks and subsystems of digital ASICs from initial design through silicon verification.
  • Perform RTL coding, verification, silicon validation, and qualification for ASIC projects.
  • Triage hardware and firmware integration issues to develop robust product solutions.
  • Contribute to the development of Inkjet and Laserjet print architecture and data path requirements.
  • Prototype ASIC designs in FPGAs or software models to support pre-silicon firmware development.
  • Drive design methodology improvements and automate engineering tools as needed.
  • Manage relationships with internal and external partners to align on specifications and documentation.

What we're looking for

  • BS or MS degree in electrical engineering or equivalent with a focus on VLSI design.
  • 8 to 10 years of ASIC or SOC design and development experience.
  • Deep knowledge of submicron semiconductor technology and embedded system design.
  • Proficiency in digital ASIC/SOC design flow from RTL to silicon characterization.
  • Familiarity with Synopsys and Cadence EDA tools for simulation, synthesis, timing, and verification.
  • Proficiency in programming languages including Verilog, SV, Python, Perl, C, and C++.
  • Experience with code base management methods such as Subversion, Git, or GitHub.
  • Working knowledge of electronic components, PCA designs, and test equipment.

More like this

Similar roles

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 46 days ago $136,000$218,500
ASIC Design Verilog System-Verilog RTL VLSI Digital Design Synthesis Timing Analysis CDC Formal Equivalence Python Perl Tcl Make files DFT mixed signal Post-Si Bringup Agentic AI
3+ yrs exp Hybrid

Senior ASIC Digital Design Engineer

General Dynamics

Remote (Annapolis Junction, MD) +3 45 days ago $142,166$150,000
RTL ASIC FPGA Synthesis Static Timing Analysis Clock Domain Crossing CDC Bus Fabric Formal Verification Simulation JIRA FinFET TSMC GlobalFoundries Samsung EDA Tools Microarchitecture Power Analysis
5+ yrs exp Remote Hybrid

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 32 days ago $168,000$264,500
Verilog System-Verilog ASIC Design RTL Logic Synthesis Timing Analysis Computer Architecture GPU Memory Systems Interconnect Networks ECO AI Workflows Autonomous Agents
8+ yrs exp

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 28 days ago $168,000$264,500
RTL Verilog ASIC Design Micro-architecture Logic Synthesis Timing Analysis VLSI Computer Architecture C++ Python Perl Bus Protocols Interconnect Networks DMA Engines Digital Systems
8+ yrs exp Hybrid

Senior ASIC Design Engineer

Nvidia

Remote (Santa Clara, CA) 9 days ago $136,000$218,500
ASIC Design RTL Design SoC Integration Logic Synthesis Timing Analysis Python Perl C++ UCIe Digital Design Verification Methodology Memory Controllers DMA Boot Controllers Fuse Controllers
5+ yrs exp Remote Hybrid

Senior ASIC Design Engineer

Cisco

Remote (San Jose, CA) 29 days ago $167,700$245,200
Verilog System Verilog ASIC Design RTL Timing Closure Clock Gating post silicon validation Scripting Micro-architecture
7+ yrs exp Remote