Silicon Design Engineer

Amd

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$166,400–$249,600 / yr
Posted
43 days ago
Freshness
Confirmed live yesterday
Closes
Jul 30, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $194k
This role $208k
$139k most similar roles pay here $261k

This role pays more than 55% of similar roles. Most pay $162,000–$226,025 — the shaded band above. At the midpoint, this role pays about $208k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Silicon Design Engineer

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As a Silicon Design Engineer, you will lead and contribute to the design, integration, verification, and characterization of advanced silicon testchips supporting FPGA and ASIC products on leading-edge process technologies. Your daily responsibilities include managing the end-to-end digital ASIC/SoC physical design cycle from RTL handoff through GDSII tapeout, including floorplanning, power planning, placement, clock tree synthesis, routing, and timing closure. You will perform physical signoff analyses such as IR drop, electromigration, and DRC/LVS verification while developing testbenches for post-silicon validation. The role requires expertise in industry-standard tools like Design Compiler, PrimeTime, Cadence Genus, Innovus, or Synopsys Fusion Compiler. You will utilize Python, Tcl, and shell scripting for automation. Technical requirements include knowledge of CMOS circuit design, semiconductor device physics, signal integrity, and experience with FinFET and Gate-All-Around nodes.

Skills

ASIC SoC RTL-to-GDS Synthesis Floorplanning Clock Tree Synthesis Static Timing Analysis PrimeTime Design Compiler Innovus Fusion Compiler DRC LVS IR Drop Electromigration Python Tcl Shell Scripting FPGA FinFET

What you'll do

  • Execute timing-aware and physical-aware synthesis flows using industry-standard tools to generate optimized netlists.
  • Manage the end-to-end digital ASIC/SoC physical design cycle from RTL handoff through GDSII tapeout.
  • Perform Static Timing Analysis (STA) to validate setup and hold margins across various PVT corners.
  • Conduct physical signoff analyses including IR drop, electromigration, noise, and DRC/LVS verification.
  • Develop verification plans and testbenches to validate chip functionality and generate post-silicon test patterns.
  • Perform post-silicon bring-up, debugging, and lab-based validation activities for new silicon.

What we're looking for

  • Candidates should hold a PhD or MS in electrical and electronics engineering or physical sciences, or a bachelor's degree with relevant experience.
  • Experience must include RTL-to-GDS implementation, design verification, and post-silicon validation.
  • Proficiency is required in digital ASIC/SoC physical design cycles including floorplanning, placement, CTS, routing, and timing closure.
  • Candidates should be skilled in using industry-standard tools such as Design Compiler, PrimeTime, Cadence Genus/Innovus, or Synopsys Fusion Compiler.
  • Experience with advanced process technologies is required, specifically FinFET (7nm/5nm/3nm) and emerging Gate-All-Around (GAA) nodes.
  • Candidates must be able to perform physical signoff analyses including IR drop, electromigration, and DRC/LVS verification.
  • Proficiency in Python, Tcl, and shell scripting for automation and flow development is required.
  • Experience with silicon bring-up, post-silicon validation, and laboratory test equipment is preferred.

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