Silicon Design Engineer

Amd

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$166,400–$249,600 / yr
Posted
89 days ago
Freshness
Confirmed live yesterday
Closes
Jul 30, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $205k
This role $208k
$138k $262k
below market most similar roles pay here above market

This role pays more than 51% of similar roles. Most pay $167,975–$241,750 — the blue band above. At the midpoint, this role pays about $208k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Silicon Design Engineer

Role Posting Log in to save

The Silicon Design Engineer will join the team to lead and contribute to the design, integration, verification, and characterization of advanced silicon testchips supporting FPGA and ASIC products on leading-edge process technologies. The role involves driving the end-to-end digital ASIC/SoC physical design cycle from RTL handoff through GDSII tapeout, including floorplanning, power planning, placement, clock tree synthesis, routing, and timing closure. Key responsibilities include performing physical signoff analyses such as IR drop, electromigration, and DRC/LVS verification, as well as developing verification plans and testbenches. The position requires expertise in CMOS circuit design, semiconductor device physics, and signal integrity. Candidates must be proficient with industry-standard tools like Design Compiler, PrimeTime, and Cadence Genus or Synopsys Fusion Compiler, along with Python, Tcl, and shell scripting.

Skills

ASIC SoC RTL-to-GDS Synthesis Floorplanning Clock Tree Synthesis CTS Routing Static Timing Analysis STA PrimeTime Design Compiler Cadence Genus Innovus Synopsys Fusion Compiler DRC LVS IR Drop Electromigration Python Tcl Shell Scripting FPGA FinFET GAA Post-Silicon Validation

What you'll do

  • Drive timing-aware and physical-aware synthesis flows to generate optimized netlists.
  • Lead the end-to-end digital ASIC/SoC physical design cycle from RTL handoff to GDSII tapeout.
  • Close SoC timing using Static Timing Analysis to validate margins across PVT corners.
  • Perform physical signoff analyses including IR drop, electromigration, noise, and DRC/LVS verification.
  • Develop verification plans and testbenches to validate chip functionality and generate post-silicon test patterns.
  • Assist with post-silicon bring-up, debugging, and lab-based validation activities.

What we're looking for

  • Experience in RTL-to-GDS implementation, design verification, and post-silicon validation.
  • Ability to lead the end-to-end digital ASIC/SoC physical design cycle from RTL handoff through GDSII tapeout.
  • Proficiency in timing-aware/physical-aware synthesis and Static Timing Analysis (STA) using industry-standard tools.
  • Experience performing physical signoff analyses including IR drop, electromigration, noise, and DRC/LVS verification.
  • Ability to develop verification plans, testbenches, and test patterns for post-silicon validation.
  • Experience with silicon bring-up, post-silicon validation, and laboratory test equipment (preferred).
  • Proficiency in Python, Tcl, and shell scripting for automation and flow development (preferred).
  • Advanced degree (PhD or MS) in electrical & electronics engineering or physical sciences, or a bachelor’s degree with relevant experience (preferred).

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