Senior Silicon Engineer

What you'll do

• Design and verify analog circuit components for custom SerDes interface IP.
• Perform mixed-signal validation of blocks to verify end-to-end calibration functionality.
• Generate timing models for analog interfaces to digital blocks.
• Conduct simulation and post-layout verification for specific macros.
• Coordinate with layout designers and other engineers to ensure design accuracy.
• Collaborate with designers to ensure the accuracy of behavioral models.

What we're looking for

• A Doctorate with 1+ years of experience, a Master's with 4+ years, or a Bachelor's with 5+ years of technical engineering experience is required.
• Ability to pass Microsoft Cloud Background Check and other government security screening requirements.
• Must provide proof of citizenship, residency, or other protected status for export control eligibility.
• Experience with deep sub-micron nodes and hands-on layout optimization (preferred).
• Ability to review DV waveforms and debug calibration related issues (preferred).
• Experience with behavioral modeling using System Verilog and LEC (preferred).
• Post silicon validation experience (preferred).
• Proficiency in Python, Perl, and other scripting languages for post silicon validation (preferred).