Principal Physical Design Engineer

Microsoft

Confirmed live yesterday Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
Salary
$142,800–$274,800 / yr
Posted
3 days ago
Freshness
Confirmed live yesterday
Closes
Mar 7, 2027

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $200k
This role $209k
$127k most similar roles pay here $291k

This role pays more than 63% of similar roles. Most pay $173,263–$226,350 — the shaded band above. At the midpoint, this role pays about $209k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 598 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 586 roles with salary data.

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At a glance

TL;DR · Principal Physical Design Engineer

The Principal Physical Design Engineer joins the Silicon, Cloud Hardware, and Infrastructure Engineering team to work on Microsoft’s Next-Gen AI SOC chip. This role focuses on delivering tool, flow, and methodology for physical design tasks at the block, sub-chip, and full-chip levels. Key responsibilities include leading Place and Route convergence recipe development, implementing strategies for Static Timing Analysis, Physical Verification, Formal Equivalency Verification, and low power verification. The engineer will also manage global clocking construction, IR-Drop/EM analysis, and IP collateral handling while providing guidance to other engineers. Required skills include proficiency in EDA tools such as Synopsys Fusion Compiler, PrimeClosure, Primetime, Formality, VCLP, Star-RC, Redhawk SC, and Cadence Innovus, alongside Siemens Calibre. Candidates should possess scripting skills in TCL and Python to optimize physical design efficiency for complex ASIC tapeouts.

What you'll do

  • Deliver tool, flow, and methodology (TFM) for physical design tasks at block, sub-chip, and full-chip levels.
  • Lead Place and Route (PnR) convergence recipe development for various design scales.
  • Develop methodologies to improve performance in static timing analysis, physical verification, and low power verification.
  • Implement functional and timing ECOs with minimal impact on the overall physical design.
  • Design and implement global clocking schemes at both SoC and sub-chip levels.
  • Manage and verify internal and external IP collaterals for use by the execution team.
  • Conduct physical design reviews to identify, resolve issues, and provide technical guidance to engineers.

What we're looking for

  • A Doctorate in Electrical Engineering, Computer Science, or related field and 3+ years of technical engineering experience.
  • A Master's Degree in Electrical Engineering, Computer Science, or related field and 6+ years of technical engineering experience.
  • A Bachelor's Degree in Electrical Engineering, Computer Science, or related field and 8+ years of technical engineering experience.
  • Ability to pass the Microsoft Cloud Background Check.
  • Must provide proof of citizenship, U.S. residency, or other protected status for export control compliance.
  • Experience in tapeouts of complex ASICs in leading edge technology (preferred).
  • 10+ years of experience in blocks level place and route (preferred).
  • Expertise in physical design EDA tools such as Synopsys Fusion Compiler, PrimeClosure, Primetime, Formality, VCLP, Star-RC, Redhawk SC, Innovus, or Siemens Calibre (preferred).

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