This role pays less than
65%
of similar roles. Most pay
$203,150–$256,387
— the shaded band above.
At the midpoint, this role pays about
$209k
versus about
$230k
for comparable roles.
Based on 240 similar postings.
Employer
About Microsoft
Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing
Microsoft currently has
598 open roles
on FindRole.
Listed pay typically runs
$119,800–$234,700
across 586 roles with salary data.
As a Principal Silicon Architect, you will provide technical leadership throughout all phases of ASIC and SoC development with a primary focus on early architecture definition and specification of Network-on-Chip, memory, and interconnect subsystems for high-performance AI and compute SoCs. You will define system-level address maps, memory hierarchy, and SoC connectivity while translating performance objectives into scalable data movement architectures. Your daily work involves evaluating third-party IP, silicon technologies, and vendor solutions while balancing power, area, and risk. You will collaborate with modeling, firmware, and software teams to ensure architectural alignment and resolve complex design tradeoffs. The role requires expertise in on-chip interconnects, memory hierarchy, security, die-to-die interconnect, debug, telemetry, boot/reset, and RAS. You must possess extensive experience in large-scale SoC design to solve critical technical challenges in high-performance computing environments.
Define early architecture and specifications for Network-on-Chip (NoC) and memory/interconnect subsystems.
Establish system-level address maps, memory hierarchies, and SoC connectivity.
Translate product performance goals into scalable data movement architectures.
Evaluate and recommend third-party IP, silicon technologies, and vendor solutions based on PPA constraints.
Partner with modeling teams to define requirements and identify system bottlenecks early in the design cycle.
Guide design and verification teams to ensure implementation fidelity to architectural intent.
Support pre-silicon validation, post-silicon bring-up, and performance characterization activities.
Resolve complex architectural issues and lead critical design trade-offs for system-level decisions.
What we're looking for
Must have a Doctorate with 3+ years experience, a Master's with 6+ years experience, or a Bachelor's with 8+ years experience in engineering/science fields.
Must have at least 10 years of architecture and design experience in large-scale SoCs.
Must possess expertise in on-chip interconnect and memory hierarchy systems.
Must have a track record of successfully designing IPs and SoCs.
Experience with security, die-to-die interconnect, debug, telemetry, boot/reset, and RAS is required.
Ability to define system-level address maps, memory hierarchy, and SoC connectivity for high-performance AI and compute SoCs.
Ability to translate performance objectives into scalable NoC, memory, and data movement architectures.
Must be able to meet export control requirements including ITAR, EAR, or EU Dual Use Regulations.
SoC
System Architecture
Silicon Roadmap
AI
CPU
GPU
NPU
Memory
Power Management
Performance Analysis
System Modeling
Firmware
Heterogeneous Compute
Security
SoC Architecture
Semiconductor Power Architecture
Power Integrity
Signal Integrity
C
C++
Scripting
Emulation
Silicon Validation
Firmware
Software Engineering
PC Architecture
Simulation
Tape-out