PLL Design Engineer

As a PLL Design Engineer within the Analog-Mixed/Signal group, you will develop cutting-edge frequency synthesizers for diverse applications including Compute, SoC, SerDes, and Cellular technologies. You will be responsible for designing and developing high-quality hard IPs to address the increasing complexity of SOC/PHY designs. Your daily work involves circuit design for PLLs and FLLs using both digital and analog approaches, specifically focusing on DCO/VCO design in RO and LC configurations, Fractional-N, SSC, and spur and jitter cancellation techniques. You will utilize System Verilog for modeling and behavioral simulations to evaluate architectural performance and loop dynamics. Required expertise includes knowledge of band gaps, bias circuits, op-amps, LDOs, and feedback compensation. You must possess deep understanding of phase noise, jitter analysis, budgeting, and scripting skills using industry-standard design tools.