Senior Engineer, PLL Design

Samsung Semiconductor

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $138,000–$206,000 / yr
Posted: 6 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Below market

How this pay compares to similar roles

Similar $193k

This role $172k

$127k $237k

below market most similar roles pay here above market

This role pays less than 72% of similar roles. Most pay $170,000–$216,250 — the blue band above. At the midpoint, this role pays about $172k versus about $193k for comparable roles.

Based on 240 similar postings.

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About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 37 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 37 roles with salary data.

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At a glance

TL;DR · Senior Engineer, PLL Design

Role Posting Log in to save

JOB TITLE: Senior Engineer, PLL Design The Senior Engineer, PLL Design will join the team to design and develop high-performance PLL and clocking subsystems for RF transceivers, SerDes, and high-speed I/O applications using advanced deep-submicron CMOS technologies. The role involves designing integer-N, fractional-N, and digital PLLs, as well as critical building blocks like VCOs, charge pumps, and loop filters. Key responsibilities include performing system-level modeling, noise analysis, and jitter budgeting, alongside driving design verification through transistor-level simulation and Monte Carlo analysis. Candidates must utilize tools such as Spectre, SpectreRF, AMS simulator, and Matlab/Simulink. Proficiency in Verilog/SystemVerilog for mixed-signal simulation and RTL design is required. The position focuses on solving complex timing and frequency challenges in high-speed communication interfaces and RF hardware.

Skills

PLL Design CMOS Matlab Simulink Verilog SystemVerilog Spectre SpectreRF AMS RF Transceivers SerDes Mixed-Signal Simulation Monte Carlo Analysis Silicon Correlation RTL Design Jitter Budgeting

What you'll do

Design PLLs and clock generation circuits for RF and SerDes applications.
Design critical PLL building blocks including VCOs, charge pumps, and loop filters.
Perform PLL system-level modeling, noise analysis, and jitter budgeting using Matlab/Simulink.
Drive design verification through transistor-level simulation, Monte Carlo analysis, and silicon correlation.
Collaborate with digital, layout, and systems teams to meet performance, power, and area targets.
Support bring-up, characterization, and debug of silicon prototypes in the lab.
Implement PLL-related digital calibration circuits using Verilog or SystemVerilog.

What we're looking for

Master's degree with 2+ years of experience or a PhD in a related field.
Extensive hands-on experience designing PLLs in deep sub-micron CMOS (5nm-28nm).
Experience designing at least one of the following: integer-N, fractional-N, digital PLL, or sub-sampling PLL topologies.
Deep understanding of PLL system theory including phase noise, jitter, loop dynamics, and spurs.
Proficiency in IC design CAD tools such as Spectre, SpectreRF, and AMS simulator.
Strong Matlab/Simulink skills for behavioral modeling and system-level analysis.
Familiarity with Verilog/SystemVerilog for mixed-signal simulation and RTL design of digital calibration circuits.
Experience with lab characterization including phase noise measurement and spectrum analysis equipment.

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