PLL Design Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$129,300–$225,300 / yr
Posted
1 day ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $202k
This role $177k
$115k $264k
below market most similar roles pay here above market

This role pays less than 65% of similar roles. Most pay $171,125–$233,137 — the blue band above. At the midpoint, this role pays about $177k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3515 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2718 roles with salary data.

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At a glance

TL;DR · PLL Design Engineer

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The PLL Design Engineer joins the Analog-Mixed/Signal group to develop cutting-edge frequency synthesizers for Compute, SoC, SerDes, and Cellular technologies. The role involves designing and developing high-quality hard IPs to address the escalating complexity of SOC/PHY designs. Key responsibilities include frequency synthesis architecture and circuit design using digital and analog approaches, including DCO/VCO design for both RO and LC types. The engineer will implement Fractional-N, SSC, and Spur and Jitter cancellation techniques while managing band gaps, bias circuits, op-amps, LDOs, and feedback compensation. Technical requirements include proficiency in System Verilog modeling, behavioral simulations, and jitter analysis. Candidates must demonstrate mastery of clocking fundamentals, loop dynamics, and scripting skills using industry-standard design tools to solve complex hardware problems.

Skills

PLL FLL Frequency Synthesis System Verilog RTL VCO DCO SerDes SoC Jitter Analysis Feedback Loop Dynamics Scripting

What you'll do

  • Develop cutting-edge frequency synthesizers for Compute, SoC, SerDes, and Cellular technologies.
  • Design PLL and FLL architectures using both digital and analog approaches.
  • Design and implement DCO/VCO circuits using RO and LC techniques.
  • Perform phase noise and jitter analysis and manage feedback loop dynamics.
  • Develop System Verilog models and perform behavioral simulations to explore architectural performance.
  • Design and debug RTL to support frequency synthesis requirements.
  • Implement spur and jitter cancellation techniques within high-quality hard IPs.

What we're looking for

  • Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design (preferred).
  • Good understanding of band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques (preferred).
  • Deep understanding of clocking fundamentals, including phase noise, jitter analysis, budgeting, and feedback loop dynamics (preferred).
  • Skilled in developing System Verilog models and performing behavioral simulations (preferred).
  • Ability to design/debug RTL (preferred).
  • Outstanding teamwork capabilities paired with strong productivity and scripting skills (preferred).
  • Experience using industry-standard design tools (preferred).

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