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Active Keyword: PLL Design Engineer Remove filter Clear all

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Senior Engineer, PLL Design

Samsung Semiconductor

San Jose, CA 11 days ago $138,000–$206,000
Actively hiring Confirmed live yesterday High trust Below market
PLL Matlab Simulink Spectre SpectreRF AMS Verilog SystemVerilog CMOS SerDes RF Mixed-Signal Monte Carlo Analysis RTL Design Spectrum Analysis Phase Noise Measurement Jitter Analysis
5+ yrs exp
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PLL Design Engineer

Apple Inc

16 days ago $175,000–$308,500
Actively hiring Confirmed live yesterday High trust Above market
10+ yrs exp
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PLL Design Integration Staff Engineer

Amd

San Jose, CA 66 days ago $166,400–$249,600
Actively hiring Confirmed live yesterday High trust Competitive pay
PLL FPGA IC Design Analog/Mixed-Signal VCO LDO Phase Interpolators SystemVerilog Vivado Clock Synthesis Digital Verification Post-Silicon Validation Floor Planning
Hybrid
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