PLL Design Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $184,700–$324,800 / yr
Posted: 5 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $208k

This role $255k

$129k $346k

below market most similar roles pay here above market

This role pays more than 96% of similar roles. Most pay $177,250–$238,787 — the blue band above. At the midpoint, this role pays about $255k versus about $208k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · PLL Design Engineer

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The PLL Design Engineer joins the Analog-Mixed/Signal group to develop cutting-edge frequency synthesizers for Compute, SoC, SerDes, and Cellular technologies. The role involves designing and developing high-quality hard IPs to address the escalating complexity of SOC/PHY designs. Key responsibilities include frequency synthesis architecture and circuit design using digital and analog approaches, specifically focusing on DCO/VCO design for both RO and LC types. The engineer will implement Fractional-N, SSC, and Spur and Jitter cancellation techniques while managing band gaps, bias circuits, op-amps, LDOs, and feedback compensation. Technical requirements include proficiency in phase noise and jitter analysis, developing System Verilog models, and performing behavioral simulations. The position requires a deep understanding of clocking fundamentals and loop dynamics to solve complex hardware problems.

Skills

PLL FLL Frequency Synthesis System Verilog RTL VCO DCO SerDes SoC Scripting Jitter Analysis Op-Amps

What you'll do

Develop cutting-edge frequency synthesizers for Compute, SoC, SerDes, and Cellular technologies.
Design PLL/FLL architectures and circuits using digital and analog approaches.
Design and optimize DCO/VCO circuits using both RO and LC techniques.
Implement Fractional-N, SSC, and spur/jitter cancellation techniques.
Perform phase noise and jitter analysis and manage feedback loop dynamics.
Develop System Verilog models and perform behavioral simulations to explore architectural performance.
Design and debug RTL to support system-level requirements.
Design and analyze band gaps, bias circuits, op-amps, and LDOs.

What we're looking for

At least 10 years of relevant experience.
Proficiency in PLL/FLL and frequency synthesis architecture and circuit design (preferred).
Understanding of band gaps, bias circuits, op-amps, LDOs, feedback, and compensation techniques (preferred).
Deep understanding of clocking fundamentals, phase noise, jitter analysis, and feedback loop dynamics (preferred).
Skill in developing System Verilog models and performing behavioral simulations (preferred).
Ability to design/debug RTL (preferred).
Strong teamwork, productivity, and scripting skills using industry-standard design tools (preferred).

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