Timing Design Engineer

Apple Inc

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Work type
On-site
Location
Beaverton, OR
Posted
40 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

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TL;DR · Timing Design Engineer

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As a Timing Design Engineer, you will join the hardware team as an ASIC STA Engineer responsible for all aspects of SoC design regarding timing. Your daily work involves timing sign-off, developing STA and sign-off flows, and owning IP and block level timing constraints from synthesis through to final sign-off. You will collaborate with RTL designers to understand design intent and clock structures, work with CAD to develop flows, and partner with physical design teams to achieve timing closure. You must innovate timing constraints to mitigate pessimism and fallouts in analysis. Required expertise includes ASIC design timing closure methodology, Primetime STA tools, and SDC constraints management. You will also utilize Tcl and Perl scripting languages while addressing process variations, signal integrity issues, and synthesis, DFT, and backend methodologies.

Skills

STA ASIC Design Timing Closure Primetime SDC Tcl Perl Synthesis DFT Backend Signal Integrity RTL Clock Structure

What you'll do

  • Perform timing sign-off for SoC designs.
  • Develop STA and sign-off flows.
  • Manage IP and block-level timing constraints from synthesis to sign-off.
  • Collaborate with RTL designers to define design intent and clock structures.
  • Work with CAD teams to develop and refine design flows.
  • Coordinate with physical design teams to close and sign-off timing.
  • Create plans to verify timing constraints.
  • Innovate timing constraints and flows to reduce pessimism and analysis fallouts.

What we're looking for

  • BS degree in a technical discipline.
  • Minimum 10 years of proven experience.
  • Detailed knowledge of the ASIC design timing closure flow and methodology (preferred).
  • At least 2+ years of experience in writing ASIC timing constraints and timing closure (preferred).
  • Expertise in STA tools (Primetime) and flow, timing corners/modes, process variations, and signal integrity issues (preferred).
  • Hands-on experience in timing/SDC constraints generation and management (preferred).
  • Proficiency in scripting languages such as Tcl and Perl (preferred).
  • Familiarity with synthesis, DFT, and backend related methodology and tools (preferred).

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