Physical Design Engineer

What you'll do

• Perform static and dynamic power reduction for advanced node technology and complex SoC designs.
• Implement low power design techniques including clock gating, power gating, and multi-voltage domain design.
• Execute floor planning, pin assignment, macro placement, and logic placement to optimize power, performance, and area.
• Perform critical Engineering Change Orders (ECOs) to resolve timing, physical verification, and power grid integrity issues.
• Complete netlist to GDS2 implementation while meeting specific schedule and design goals.
• Conduct static timing analysis, IR/IVD analysis, and debug LVC/DRC violations for signoff closure.
• Develop scripts using TCL, Perl, or Python to automate CAD tool flows and improve efficiency.
• Resolve and improve design and flow issues related to physical design throughout the development cycle.

What we're looking for

• Master's degree or foreign equivalent in Computer Engineering or a related field.
• 3 years of experience in the job offered or a related occupation.
• Experience using Innovus or Fusion Compiler APR tools for implementation design and physical design workflows.
• Experience tuning implementation design flows to improve power, performance, and area.
• Experience performing static timing analysis, IR/IVD analysis, and resolving LVC/DRC violations.
• Experience performing physical design on advanced technology nodes (7nm and below) with knowledge of modern CMOS technology.
• Experience in block level physical design including floor planning, placement, clock tree synthesis, routing, and ECO implementation.
• Proficiency in scripting languages such as TCL, Perl, or Python to implement automated techniques.