Infra Systems Physical Architect

What you'll do

• Design and optimize floorplan-driven Network on Chip (NoC) architectures for high-performance SoCs.
• Develop custom methodologies to achieve optimal latency, area, performance, and power goals.
• Analyze and improve functional and test (DFT) mode constraints for synthesis and physical design processes.
• Create recipes for physically aware synthesis, special placement strategies, and optimized floorplanning.
• Design advanced clocking solutions such as mesh clock trees and source sync clock routing.
• Perform power planning, analysis, and timing closure for multi-mode clock (MMMC) designs.
• Develop scripts and tools using Python, Perl/TCL, and C to automate design workflows.
• Evaluate area, latency, and timing metrics to plan physically aware NoC architectures for future products.

What we're looking for

• Bachelor's degree with 6+ years of experience, Master's with 5+ years, or PhD with 4+ years in ASIC design, verification, validation, or integration.
• Experience in NoC implementation, AMBA protocols, and cache coherency mechanisms.
• Expertise in physical design including floorplanning, clock tree planning (spine/mesh), and custom placement and routing.
• Proficiency in physical aware synthesis, physical aware DFT, and power domain analysis.
• Experience with timing analysis, signal integrity for MMMC designs, and formal verification.
• Deep knowledge of scripting languages including Python, PERL/TCL, Linux/Unix shell, and C.
• Familiarity with industry tools such as Design Compiler, Fusion Compiler, Genus, Primetime, PrimePower, or Innovus is preferred.