Infra Systems Physical Architect

What you'll do

• Design and optimize floorplan-driven Network on Chip (NoC) architectures for high-performance SoCs.
• Develop custom methodologies and recipes for physical-aware synthesis and special placement strategies.
• Analyze and improve functional and test (DFT) mode constraints for synthesis and place and route processes.
• Design special clocking solutions, including mesh clock trees, and perform power planning for low-power designs.
• Perform timing optimization and closure with signal integrity for multi-mode multi-corner (MMMC) designs.
• Estimate and plan physically aware NoC architectures by analyzing area, latency, timing, and power metrics.
• Utilize scripting languages including Python, PERL/TCL, and Linux/Unix shell to automate design tasks.

What we're looking for

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, or integration experience.
• Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, or integration experience.
• PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, or integration experience.
• Deep knowledge of scripting and software languages including Python, PERL/TCL, Linux/Unix shell, and C.
• Experience in NoC implementation, AMBA Protocol, and cache coherency mechanisms (preferred).
• Experience in constraining and timing analysis, physical aware synthesis, physical aware DFT, and physical design (preferred).
• Experience in clock tree planning, custom placement and routing, and formal verification (preferred).
• Experience with Design Compiler, Fusion Compiler, Genus, Primetime, Prime Power, or Innovus (preferred).