HBM PHY System Architect

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $164,000–$246,000 / yr
Posted: 65 days ago
Freshness: Confirmed live 2 days ago
Closes: Jan 5, 2027
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $209k

This role $205k

$148k most similar roles pay here $260k

This role pays more than 50% of similar roles. Most pay $168,750–$248,637 — the shaded band above. At the midpoint, this role pays about $205k versus about $209k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 621 open roles on FindRole.

Listed pay typically runs $147,900–$222,500 across 601 roles with salary data.

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At a glance

TL;DR · HBM PHY System Architect

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HBM PHY System Architect will join the mixed-signal IP design team to develop high-speed, high-performance, and low-power HBM Phys. The role involves owning the HBM PHY architecture and system definition while driving end-to-end solutions that meet specific performance, power, area, and reliability targets. Key responsibilities include managing system timing budgets across on-die and off-chip interfaces, leading cross-functional architectural trade-offs with SoC, memory, package, and validation teams, and ensuring alignment with product roadmap requirements. The ideal candidate possesses expertise in JEDEC memory standards like HBM, LPDDR, and DDR, along with skills in link budgeting, timing closure, margin analysis, and PHY training methodologies. Technical competencies include signal integrity, power integrity, mixed-signal design principles, and proficiency in Unix/Linux environments using scripting languages such as Perl, TCL, or Python to solve complex high-speed memory interface challenges.

Skills

HBM DDR LPDDR PHY ASIC Signal Integrity Power Integrity Mixed-Signal Design Unix Linux Python TCL Perl Timing Closure High-Speed Interfaces

What you'll do

Own the HBM PHY architecture and system definition to meet performance, power, area, and reliability targets.
Develop and manage system timing budgets for on-die and off-chip interfaces.
Lead cross-functional architectural trade-offs with SoC, memory, package, and validation teams.
Deliver high-performance HBM PHY solutions through technical leadership and innovation.
Perform link budgeting, timing closure, margin analysis, and PHY training methodologies.
Ensure robust operation of high-speed interfaces across all operating conditions.
Address signal integrity, power integrity, and manufacturing challenges for high-speed memory links.

What we're looking for

Bachelor's degree in Electrical Engineering or a related field is required.
Master's degree in Electrical Engineering or a related field is preferred.
5+ years of experience in HBM PHY architecture and design for high-performance memory interfaces.
6+ years of ASIC design, verification, validation, or integration experience with a Bachelor's degree.
5+ years of ASIC design, verification, validation, or integration experience with a Master's degree.
4+ years of ASIC design, verification, validation, or integration experience with a PhD.
Strong understanding of JEDEC memory standards including HBM, LPDDR, and DDR.
Expertise in link budgeting, timing closure, margin analysis, and PHY training for high-speed interfaces.

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