DDR PHY System Design Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$140,000–$210,000 / yr
Posted
93 days ago
Freshness
Confirmed live yesterday
Closes
Dec 7, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $188k
This role $175k
$130k most similar roles pay here $230k

This role pays less than 60% of similar roles. Most pay $159,525–$216,250 — the shaded band above. At the midpoint, this role pays about $175k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · DDR PHY System Design Engineer

The DDR PHY System Design Engineer joins the mixed-signal IP design team to develop high-speed, high-performance, and low-power DDR Phys for products targeting 5G, AI/ML, compute, and automotive applications. This role involves ownership of DDR PHY system architecture, including developing on-die and off-chip timing budgets while delivering solutions for specific product needs from early concepts through final chip production and validation. The ideal candidate possesses expertise in JEDEC standards such as LPDDR, PCDDR, and HBM, along with deep knowledge of link-budgets, training, signal integrity, and power delivery for server products. Technical proficiency includes experience with mixed-signal designs on modern process nodes and the ability to write scripts using Unix, Perl, or TCL. The role focuses on solving complex high-speed interface challenges while ensuring design-for-yield and production success in advanced memory systems.

What you'll do

  • Own the analysis and architecture of DDR PHY systems for 5G, AI/ML, and automotive products.
  • Develop comprehensive system timing budgets for both on-die and off-chip components.
  • Deliver high-performance, low-power solutions tailored to specific product requirements.
  • Manage the full lifecycle of design from initial concepts to final chip production and validation.
  • Implement JEDEC standards including LPDDR, PCDDR, and HBM into PHY system designs.
  • Manage link budgets and training protocols for high-speed interfaces.
  • Address signal integrity and power delivery challenges for server products.
  • Write scripts using Unix, Perl, or TCL to support design and automation tasks.

What we're looking for

  • Bachelor's degree in Electrical Engineering or a related field is required.
  • Master's degree in Electrical Engineering or a related field is preferred.
  • 5 to 10 years of experience in DDR PHY system design and architecture.
  • Strong knowledge of JEDEC DDR standards including LPDDR, PCDDR, and HBM.
  • Strong knowledge of link budgets and training procedures.
  • Proficiency in Unix, Perl, and TCL scripting is required.
  • Knowledge of signal integrity, power delivery, and mixed-signal designs for high-speed links is preferred.
  • Ability to collaborate effectively across global teams with strong communication skills.

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