DDR PHY System Design Engineer (San Diego, US)

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$140,000–$210,000 / yr
Posted
5 days ago
Closes
Dec 7, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $176k
This role $175k
$132k most similar roles pay here $218k

This role pays more than 54% of similar roles. Most pay $149,500–$202,675 — the shaded band above. At the midpoint, this role pays about $175k versus about $176k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 749 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 429 roles with salary data.

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At a glance

TL;DR · DDR PHY System Design Engineer (San Diego, US)

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Qualcomm Technologies is seeking a senior system architect to join its mixed-signal IP design team, focusing on the development of high-speed and low-power DDR PHYs for 5G, AI/ML, compute, and automotive applications. The role involves analyzing and owning DDR PHY systems and architectures, developing timing budgets both on-die and off-chip, and delivering cutting-edge solutions to meet product requirements. Ideal candidates will have 5-10 years of experience in DDR PHY system design with expertise in JEDEC standards, link-budgets, and trainings. Strong communication skills are essential for collaboration across global teams. Preferred qualifications include knowledge of signal integrity and power delivery, familiarity with advanced process technology nodes, and proficiency in Unix/Perl/TCL scripting.

Skills

Perl TCL Unix DDR DRAM PHY JEDEC LPDDR PCDDR HBM signal integrity power integrity link-budgets trainings design-for-yield high-speed interface mixed-signal designs

What you'll do

  • Analyze and own DDR PHY system and architecture.
  • Develop on-die and off-chip system timing budgets.
  • Lead the delivery of best-in-class solutions for product needs.
  • Apply strong knowledge in JEDEC DDR standards to design.
  • Understand link-budgets and trainings thoroughly.

What we're looking for

  • 5-10 years of experience in DDR PHY system design/architecture
  • Expertise in JEDEC DDR standards and their implications for DDR PHY design
  • Proficient in link-budget analysis and training methodologies
  • Strong communication skills with proven ability to collaborate globally
  • Knowledge of signal integrity, power delivery, and mixed-signal designs
  • Comfortable with Unix/Perl/TCL scripting for automation tasks

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