Digital ASIC Design Engineer for Mixed-Signal IPs

Qualcomm

Confirmed live 2 days ago Trusted

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$115,600–$173,400 / yr
Posted
71 days ago
Freshness
Confirmed live 2 days ago
Closes
Dec 29, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $193k
This role $144k
$102k most similar roles pay here $244k

This role pays less than 90% of similar roles. Most pay $170,277–$216,250 — the shaded band above. At the midpoint, this role pays about $144k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Digital ASIC Design Engineer for Mixed-Signal IPs

Role Posting Log in to save

Digital ASIC Design Engineer for Mixed-Signal IPs joins the Mixed-Signal IP team to develop next-generation components including DAC, ADC, and PLLs for integration across various product lines. In this role, you will collaborate with cross-functional teams to architect, design, implement, and validate complex IP blocks while managing the full ASIC design flow from RTL through GDSII. Daily responsibilities include developing micro-architecture, implementing RTL, performing lint checking, clock domain crossing analysis, and designing DFT logic for stuck-at and transition delay fault coverage. You will utilize industry-standard tools such as VCS, Fusion Compiler, PrimeTime, Power Compiler, and Spyglass to optimize power, performance, and area. The role requires expertise in computer architecture, digital signal processing, and low-power design techniques while utilizing Python or Perl for automation scripts to solve complex mixed-signal integration challenges.

Skills

RTL ASIC Design Mixed-Signal IP Digital Signal Processing VCS Fusion Compiler PrimeTime Power Compiler Spyglass DFT STA CDC Python Perl GDSII Synthesis Formal Verification Floorplanning Pre-silicon Simulation

What you'll do

  • Architect and define the digital design of mixed-signal IPs such as DACs, ADCs, and PLLs.
  • Develop micro-architecture and implement RTL for complex mixed-signal IP blocks.
  • Apply advanced techniques in computer architecture and DSP to optimize power, performance, and area.
  • Perform lint checking, clock domain crossing analysis, synthesis, formal verification, and static timing analysis.
  • Design and analyze DFT logic including ATPG for stuck-at and transition delay fault coverage.
  • Create comprehensive hardware specifications and design documentation.
  • Collaborate with physical design teams to support floorplanning, placement, and timing closure.
  • Support SoC integration and debug through pre-silicon simulation and post-silicon bring-up.

What we're looking for

  • A Bachelor's degree in Science, Engineering, or a related field with 2+ years of ASIC design experience is required.
  • A Master's degree in Science, Engineering, or a related field with 1+ year of ASIC design experience is required.
  • A PhD in Science, Engineering, or a related field is accepted as an alternative educational qualification.
  • Candidates must have 3+ years of experience in RTL and ASIC design.
  • Proficiency with front-end tools like VCS, Fusion Compiler, PrimeTime, Power Compiler, DFT Compiler, and Spyglass is required.
  • Experience in low-power digital design techniques and high-speed digital circuit design is preferred.
  • Expertise in computer architecture, digital signal processing, and algorithm development is preferred.
  • Ability to develop automation scripts and design productivity tools using Python or Perl is preferred.

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