CPU Design Timing Engineer

What you'll do

• Drive timing closure for the CPU project in collaboration with micro-architects and implementation engineers.
• Develop and improve timing flows and analysis scripts in coordination with the CAD team.
• Perform static timing analysis using tools such as PrimeTime or Tempus.
• Manage timing analysis across multiple clock and power domains including noise analysis and mitigation.
• Implement variation modeling to ensure design reliability.
• Author SDC commands for clock definitions, timing exceptions, and IO constraints.
• Utilize TCL, Perl, or Python to automate and improve engineering efficiency.
• Analyze and plot data to represent complex timing results and metrics.

What we're looking for

• Minimum BS degree and 10+ years of relevant experience.
• Experience with static timing analysis tools such as PrimeTime or Tempus.
• Experience with timing analysis involving multiple clock/power domains, noise analysis, and fixing design noise.
• Experience with variation modeling.
• Experience with TCL and either Perl or Python.
• Experience with SDC command usage including clock definitions, timing exceptions, and IO constraints.
• Experience performing timing analysis in high-speed digital designs like CPUs (preferred).
• Understanding of physical design tools, deep sub-micron technologies, and CPU microarchitecture (preferred).