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Active Keyword: CPU Server Physical Design Timing Engineer Remove filter Clear all

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CPU Server Physical Design Timing Engineer

Qualcomm

Santa Clara, CA 3 days ago $142,200–$213,400
Actively hiring Posted this week Verified listing Competitive pay
TCL Perl Python Prime-time Tempus ICC2 Innovus STA AOCV POCV CTS TCL scripting Perl scripting Python scripting ASIC back-end design flows Cross-talk noise Signal Integrity Layout Parasitic Extraction Feed through handling
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CPU Server Physical Design Timing Engineer

Qualcomm

Santa Clara, CA 97 days ago $198,700–$298,100
Actively hiring Above market
TCL Perl Python Prime-time Tempus ICC2 Innovus STA AOCV POCV CTS ASIC Cross-talk noise Signal Integrity Layout Parasitic Extraction
Save