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Active Keyword: ASIC DFT Technical Leader Remove filter Clear all

8 of up to 20 (filtered)

ASIC DFT Engineering Technical Leader

Cisco

San Jose, CA +2 5 days ago $186,900–$267,700
Actively hiring Confirmed live today Posted this week High trust Above market
ASIC Implementation Design-for-Test ATPG Tessent TestMax Tetramax Verilog Gate Level Simulation VCS SDF Scan Insertion JTAG Tcl Python Perl Static Timing Analysis Post-Silicon Validation
8+ yrs exp Hybrid
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ASIC DFT Technical Leader

Cisco

San Jose, CA +1 8 days ago $186,900–$267,700
Actively hiring Confirmed live today High trust Above market
DFT ASIC Verilog System Verilog ATPG Jtag Scan BIST TestMax Tetramax Tessent PrimeTime VCS Gate Level Simulation Static Timing Analysis Post-Silicon Validation ATE P1687 RTL Physical Design
10+ yrs exp Hybrid
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ASIC Post silicon DFT Technical Leader

Cisco

Austin, TX +1 14 days ago $177,600–$257,400
Actively hiring Confirmed live yesterday Trusted Competitive pay
ASIC DFT Post-Silicon Validation Verilog VCS Gate Level Simulation ATE Patterns P1687 Static Timing Analysis DFT CAD Hardware Bring-up IP Integration Test Architecture Methodology Infrastructure
10+ yrs exp Hybrid
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ASIC DFT DV Technical Leader

Cisco

San Jose, CA 14 days ago $186,900–$267,700
Actively hiring Confirmed live today High trust Above market
System Verilog UVM DFT Python TCL Perl Verdi JTAG MBIST Scan Architecture Boundary Scan ATE RTL Physical Design post silicon validation
8+ yrs exp Hybrid
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ASIC DFT Technical Leader, CDC

Cisco

San Jose, CA +2 14 days ago $186,900–$267,700
Actively hiring Confirmed live today High trust Above market
ASIC RTL CDC RDC SDC VCS SVA SystemVerilog Synthesis Gate Netlists
8+ yrs exp Hybrid
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ASIC DFT Technical Leader

Cisco

San Jose, CA 41 days ago
Actively hiring Confirmed live yesterday Low trust
Verilog System Verilog ATPG JTAG Scan BIST VCS TestMax Tetramax Tessent PrimeTime Gate Level Simulation Static Timing Analysis post silicon validation RTL Physical Design EDA Tools
10+ yrs exp Hybrid
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ASIC DFT Technical Leader, MBIST

Cisco

San Jose, CA +1 54 days ago $214,100–$309,800
Actively hiring Confirmed live yesterday High trust Above market
ASIC DFT MBIST Python TCL Perl Verilog System Verilog Synopsys DesignWare SMS TestMax Mentor Graphics Tessent SRAM DRAM
10+ yrs exp Hybrid
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ASIC DFT Technical Leader

Cisco

San Jose, CA +1 84 days ago $186,900–$267,700
Actively hiring Confirmed live today Low trust Above market
DFT ASIC Verilog System Verilog ATPG Jtag Scan BIST TestMax Tetramax Tessent PrimeTime VCS Gate Level Simulation Static Timing Analysis Post-Silicon Validation P1687 EDA Tools
10+ yrs exp Hybrid
Save