ASIC DFT Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Fort Collins, COSan Jose, CA
Salary
$129,400–$207,000 / yr
Employment
Full-time
Posted
2 days ago
Freshness
Confirmed live yesterday
Closes
Oct 24, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $204k
This role $168k
$115k most similar roles pay here $264k

This role pays less than 77% of similar roles. Most pay $177,250–$231,737 — the shaded band above. At the midpoint, this role pays about $168k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 172 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 125 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · ASIC DFT Engineer

Role Posting Log in to save

The ASIC DFT Engineer joins the ASIC Product Division to lead DFT programs from chip level specification through implementation, verification, and production release. This role involves managing SoC DFT activities including architecture, test insertion, pattern generation, coverage improvement, post-silicon debug, and yield improvement. The engineer will collaborate with Physical Design and STA teams for timing closure while interacting with external customers and global manufacturing teams. Key responsibilities include implementing Scan, MBIST, TAP, LBIST, IO, and SerDes features, as well as automating test vector generation flows. Required technical expertise includes Verilog coding, Mentor TestKompress, TetraMax, Fastscan, Tessent SSN, and knowledge of IEEE1149.1, IEEE1149.6, IEE1687, IJTAG, ICL, and PDL. The role addresses testability challenges in 3nm and beyond technologies while ensuring high quality metrics through statistical process control and data analysis techniques.

Skills

DFT ATPG Scan MBIST LBIST Verilog Tessent SSN Mentor TestKompress TetraMax Fastscan STA IEEE1149.1 IEEE1149.6 IEE1687 IJTAG ICL PDL SerDes DDR PCIe CXL

What you'll do

  • Define DFT specifications based on customer requirements and product quality goals.
  • Implement DFT features including Scan, MBIST, TAP, LBIST, IO, and SerDes integration.
  • Generate, verify, and debug test vectors before tape release.
  • Collaborate with Physical Design and STA teams to achieve DFT mode timing closure.
  • Perform silicon bring-up, failure analysis, and yield improvement activities on ATE.
  • Develop automated flows for DFT and test vector generation.
  • Innovate new DFT solutions to solve testability problems for advanced nodes like 3nm.
  • Manage project deliverables across cross-functional teams including Test Engineering and Manufacturing.

What we're looking for

  • Bachelor's degree and 8+ years of related experience, or a Master's degree and 6+ years of related experience.
  • Strong DFT background including IO/Analog DFT, ATPG, Scan, and BIST.
  • Experience in scan insertion and compression using tools like DFT Compiler or Mentor TestKompress.
  • Proficiency in ATPG vector generation, simulation, and debugging using tools like TetraMax or Fastscan.
  • Experience in Verilog coding, testbench generation, and simulation.
  • Knowledge of memory BIST verification for embedded memories (SRAM, CAM, eDRAM, ROM).
  • Familiarity with IEEE1149.1, IEEE1149.6, IEE1687, IJTAG, ICL, and PDL.
  • Experience with ATE, Serdes, DDR, PCIe, ENET, CXL, or Tessent SSN (preferred).

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