ASIC DFT Engineer

Broadcom

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$141,300–$226,000 / yr
Posted
39 days ago
Closes
Oct 24, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $187k
This role $184k
$131k most similar roles pay here $236k

This role pays more than 53% of similar roles. Most pay $158,275–$216,250 — the shaded band above. At the midpoint, this role pays about $184k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 61 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 60 roles with salary data.

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At a glance

TL;DR · ASIC DFT Engineer

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Broadcom's ASIC Product Division in San Jose seeks a senior DFT engineer to join their dynamic team, focusing on the design and implementation of SoC test strategies. This role involves defining DFT specifications based on Broadcom and customer requirements, conducting pattern generation and verification at chip level, and supporting rapid bring-up at ATE with RMA assistance. The candidate will also validate and debug test vectors both pre-tape release and during silicon bring-up phases, assist in failure analysis and yield improvement efforts, and collaborate closely with IP DFT engineers and other stakeholders. Key skills include experience with TetraMax and Fastscan for logic BIST design, Verilog coding, IEE1687 standards, and statistical process control techniques to enhance silicon quality metrics. Additional expertise in ATE, Serdes, DDR, PCIE, ENET, CXL IOBIST verification is beneficial.

Skills

TetraMax Fastscan Verilog IEEE1687 IJTAG ICL PDL Python Statistical_Process_Control ATE Serdes DDR PCIE ENET CXL I/O_BIST DFT Testbench_Generation Simulation Debugging Root_Cause_Analysis

What you'll do

  • Define DFT specifications for ASICs based on Broadcom and customer requirements.
  • Generate and verify test vectors before tape release for chip-level testing.
  • Validate and debug test vectors during silicon bring-up phase at ATE.
  • Assist in failure analysis, diagnostics, and yield improvement efforts post-silicon.
  • Innovate new DFT solutions to address testability issues in advanced nodes.

What we're looking for

  • 12+ years of experience in ASIC DFT or related field.
  • Expertise in Logic BIST design using TetraMax and Fastscan tools.
  • Proficient in Verilog coding, testbench generation, and simulation.
  • Strong knowledge of IEE1687, IJTAG, ICL, and PDL standards.
  • Excellent problem-solving skills for DFT challenges and yield improvement.
  • Experience with statistical process control and data analysis techniques.

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