ASIC DFT Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Posted
17 days ago
Freshness
Confirmed live yesterday
Closes
Oct 24, 2026
Nearby
99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $195k
$141k most similar roles pay here $239k

This listing doesn't post a salary. Most similar roles pay $172,000–$217,500.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

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At a glance

TL;DR · ASIC DFT Engineer

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The ASIC DFT Engineer joins the ASIC Product Division to lead design for test programs from chip level specification through implementation, verification, and production release. This role involves managing SoC DFT activities including architecture, test insertion, pattern generation, coverage improvement, and post-silicon debug to meet product test metrics. The engineer will work on Scan, MBIST, TAP, LBIST, IO, and SerDes integration while collaborating with Physical Design and STA teams for timing closure. Key technical requirements include expertise in Verilog, Mentor TestKompress, TetraMax, Fastscan, and Tessent SSN. Candidates must possess skills in ATPG vector generation, memory BIST verification for SRAM or CAM, and knowledge of IEEE1149.1, IEEE1149.6, IEE1687, and IJTAG. The role addresses critical testability challenges in 3nm and beyond technologies while ensuring silicon yield improvements through data analysis and automated flow development.

Skills

DFT ATPG Scan Insertion MBIST TAP LBIST Verilog Tessent SSN Mentor TestKompress TetraMax Fastscan IEEE1149.1 IEEE1149.6 IEE1687 IJTAG ICL PDL STA SerDes DDR PCIe

What you'll do

  • Define DFT specifications based on customer requirements and product quality goals.
  • Implement and integrate Scan, MBIST, TAP, LBIST, IO, and SerDes features into the SoC.
  • Generate, verify, and debug test vectors before tape release and during silicon bring-up.
  • Collaborate with Physical Design and STA teams to achieve DFT mode timing closure.
  • Perform post-silicon debug, failure analysis, and yield improvement activities.
  • Automate DFT and test vector generation flows to improve efficiency.
  • Develop innovative DFT solutions for advanced nodes such as 3nm and beyond.
  • Manage project timelines and prioritize deliverables across cross-functional engineering teams.

What we're looking for

  • A Bachelor's degree and 12+ years of related experience are required.
  • A Master's degree and 10+ years of related experience are accepted as an alternative qualification.
  • Candidates must have a strong background in DFT, including IO, Analog DFT, ATPG, Scan, and BIST.
  • Experience with scan insertion and compression using tools like DFT Compiler or Mentor TestKompress is required.
  • Proficiency in ATPG vector generation, simulation, and debugging using tools like TetraMax or Fastscan is required.
  • Candidates must have experience in Verilog coding, testbench generation, and simulation.
  • Knowledge of IEEE1149.1, IEEE1149.6, IEE1687, IJTAG, ICL, and PDL is required.
  • Strong knowledge of analog and digital circuit design, device physics, and silicon yield improvement techniques is required.

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