CPU DFT Engineer

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$142,200–$213,400 / yr
Posted
43 days ago
Freshness
Confirmed live 2 days ago
Closes
Jan 26, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $189k
This role $178k
$132k most similar roles pay here $235k

This role pays less than 61% of similar roles. Most pay $162,000–$216,618 — the shaded band above. At the midpoint, this role pays about $178k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · CPU DFT Engineer

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As a CPU DFT Engineer within the CPU Engineering group, you will collaborate with chip architects, designers, implementation engineers, and test engineers to verify DFT and DFD architecture, implementation, and test plans for mixed signal and digital VLSI designs. You will be responsible for creating or overseeing the creation of test vectors, validating that DFT requirements are met, and working with designers to improve debug observability, flexibility, and test coverage. This role involves a ground-up implementation of a new chip architecture. Key technical requirements include proficiency in Verilog, VHDL, TCL, Perl, Python, and Shell scripting. You will utilize Mentor Tessent tools while applying knowledge of JTAG, ATPG, scan compression, IEEE 1500, MBIST, and LBIST to ensure post-PD designs meet specifications for large, complex designs within the semiconductor domain.

Skills

DFT ATPG Mentor Tessent Verilog VHDL TCL Python Shell Scripting Perl JTAG MBIST LBIST Scan Compression IEEE 1500 VLSI Test Pattern Translation

What you'll do

  • Verify DFT and DFD architecture, implementation, and test plans for mixed signal and digital VLSI designs.
  • Create or oversee the creation of test vectors for complex chip designs.
  • Validate that all DFT requirements are met throughout the design process.
  • Collaborate with designers to improve test coverage, debug observability, and hardware flexibility.
  • Verify that post-physical design (PD) layouts meet established DFT requirements.
  • Execute and run tests in coordination with test personnel when necessary.
  • Implement SoC level verification on large, complex chip designs.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 1+ year of experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • At least 5 years of practical experience in Electrical/Computer Engineering.
  • At least 3 years of practical experience with test or DFT.
  • Strong fundamentals in digital ASIC design using Verilog or VHDL.
  • Experience with Mentor Tessent tools and other commercial test generation tools for large complex designs.
  • Proficiency in TCL, Perl, Python, and Shell scripting.

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