CPU DFT Engineer

Qualcomm

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$142,200–$213,400 / yr
Posted
8 days ago
Closes
Dec 6, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $193k
This role $178k
$130k most similar roles pay here $253k

This role pays less than 62% of similar roles. Most pay $168,362–$217,687 — the shaded band above. At the midpoint, this role pays about $178k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 753 open roles on FindRole.

Listed pay typically runs $152,950–$231,000 across 436 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · CPU DFT Engineer

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As a DFT Engineer at Qualcomm Technologies, Inc., you will join a dynamic team of chip architects and designers to verify and implement Design for Test (DFT) and Design for Debug (DFD) architectures for both mixed-signal and digital VLSI designs. Your daily responsibilities include creating test vectors, validating DFT requirements, increasing test coverage, and collaborating with designers to enhance debug observability. You will use Mentor Tessent tools and have hands-on experience with Verilog or VHDL, TCL, Perl/Python, and Shell scripting. Ideal candidates possess a strong background in digital ASIC design, test generation for large complex designs, and DFT techniques such as JTAG, ATPG, and MBIST. This role offers the opportunity to contribute to a new chip architecture from the ground up, impacting the verification of SOC level designs on large-scale projects.

Skills

Verilog VHDL Mentor Tessent tools TCL Perl Python Shell scripting JTAG ATPG IEEE 1500 Standard MBIST LBIST SOC level verification Test compression software

What you'll do

  • Create and validate test vectors for VLSI designs.
  • Ensure DFT requirements are met in post-PD design phases.
  • Collaborate with designers to enhance test coverage and observability.
  • Use Mentor Tessent tools for DFT implementation and verification.
  • Oversee SOC level verification on large, complex designs.
  • Assist test personnel by running tests as required.

What we're looking for

  • Bachelor’s degree in Electrical/Computer Engineering and 5+ years of practical experience.
  • Strong fundamentals in digital ASIC design with Verilog or VHDL experience.
  • Experience with test, DFT, and debug for mixed signal and digital VLSI designs.
  • Proficiency using Mentor Tessent tools and defining SOC level verification on large designs.
  • Hands-on expertise with commercial test generation tools for complex designs.

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