CPU DFT Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $147,900–$221,900 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Closes: Mar 16, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $200k

This role $185k

$134k $277k

below market most similar roles pay here above market

This role pays less than 63% of similar roles. Most pay $167,975–$231,625 — the blue band above. At the midpoint, this role pays about $185k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · CPU DFT Engineer

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The CPU DFT Engineer joins the CPU Engineering group to verify and implement DFT and DFD architectures for mixed signal and digital VLSI designs. Working on a ground-up implementation of a new chip architecture, the engineer collaborates with architects, designers, and test engineers to ensure test plans become reality. Key responsibilities include creating test vectors, validating DFT requirements, increasing test coverage, and debugging observability. The role requires proficiency in Verilog, VHDL, TCL, Perl, Python, and Shell scripting, alongside experience with Mentor Tessent tools. Candidates must demonstrate expertise in ASIC test, JTAG, ATPG, scan compression, IEEE 1500, MBIST, and LBIST. This position focuses on defining and implementing SOC level verification on large designs to solve complex hardware testing and debug problems.

Skills

DFT ASIC Design Verilog VHDL Mentor Tessent TCL Python Perl Shell Scripting JTAG ATPG Scan Compression MBIST LBIST IEEE 1500

What you'll do

Create or oversee the creation of test vectors for mixed signal and digital VLSI designs.
Validate that all DFT requirements are being met throughout the design process.
Work with designers to increase test coverage, debug observability, and design flexibility.
Verify that post-PD designs meet all specified DFT requirements.
Execute tests as needed to support test personnel and project goals.
Implement SOC level verification on large, complex chip architectures.
Use Mentor Tessent tools and scripting languages like TCL, Perl, and Python for design tasks.

What we're looking for

BA/BS in Electrical/Computer Engineering with 5+ years of practical experience.
Master's degree in a related field with 1+ year of relevant work experience.
PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Strong fundamentals in digital ASIC design with experience using Verilog or VHDL.
3+ years of practical experience with test or DFT.
Experience with ASIC test, DFT, and debug.
Experience using Mentor Tessent tools.
Experience with TCL, Perl/Python, and Shell scripting.
Experience defining and implementing SOC level verification on large designs.
Hands-on expertise with commercial test generation tools for large complex designs (preferred).
Strong knowledge of JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500, and MBIST/LBIST (preferred).
Experience running test compression software (preferred).

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