ASIC DFT Engineer

Cisco

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CAAustin, TX
Salary
$167,700–$245,200 / yr
Employment
Full-time
Posted
30 days ago
Freshness
Confirmed live yesterday
Closes
Nov 6, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $205k
This role $206k
$138k most similar roles pay here $262k

This role pays less than 51% of similar roles. Most pay $177,250–$233,050 — the shaded band above. At the midpoint, this role pays about $206k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 202 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 156 roles with salary data.

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At a glance

TL;DR · ASIC DFT Engineer

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As an ASIC DFT Engineer within the Silicon One development organization, you will join the Common Hardware Group to develop next-generation networking chips. You will collaborate with front-end RTL and back-end physical design teams to define requirements early in the cycle, drive the DFT and quality process through implementation, and manage post-silicon validation phases. Your daily work involves implementing hardware Design-for-Test features for ATE, in-system test, debug, and diagnostics while developing innovative DFT IP for new silicon device models like bare die and stacked die. You will utilize tools such as TestMax, Tetramax, Tessent, and PrimeTime, while working with Jtag protocols, Scan, BIST architectures, Verilog, SystemVerilog, and VCS simulators. The role focuses on solving complex testability challenges for high-performance networking hardware through advanced DFT CAD development and gate-level simulation.

Skills

DFT ATPG Scan BIST JTAG Verilog System Verilog VCS TestMax Tetramax Tessent PrimeTime Static Timing Analysis Gate Level Simulation Post-Silicon Validation P1687 RTL

What you'll do

  • Implement Hardware Design-for-Test (DFT) features to support ATE, in-system test, debug, and diagnostics.
  • Develop innovative DFT IP in collaboration with multi-functional teams for full chip design integration.
  • Drive DFT requirements early in the design cycle by collaborating with front-end RTL and back-end physical design teams.
  • Manage the DFT and quality process through the entire implementation flow and post-silicon validation phases.
  • Create innovative hardware DFT and physical design aspects for new silicon device models, including bare die and stacked die.
  • Develop reusable test and debug strategies to streamline production and testing processes.
  • Perform gate-level simulation and debugging using tools like VCS to validate test logic.
  • Execute post-silicon validation and debug using ATE patterns and specialized DFT tools.

What we're looking for

  • Bachelor's or Master's degree in Electrical or Computer Engineering required.
  • At least 7 years of experience in the field is required.
  • Experience with Jtag protocols, Scan and BIST architectures (including memory BIST and boundary scan) is required.
  • Experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime is required.
  • Experience with gate level simulation and debugging using VCS or other simulators is required.
  • Post-silicon validation and debug experience with ATE patterns and P1687 is required.
  • Verilog design experience for custom DFT logic and IP integration is preferred.
  • Familiarity with functional verification, DFT CAD development, Static Timing Analysis, and System Verilog Logic Equivalency checking is preferred.

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