DFT Lead Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$143,800–$230,000 / yr
Posted
31 days ago
Freshness
Confirmed live yesterday
Closes
Feb 7, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $200k
This role $187k
$133k most similar roles pay here $240k

This role pays less than 65% of similar roles. Most pay $175,488–$223,750 — the shaded band above. At the midpoint, this role pays about $187k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · DFT Lead Engineer

Role Posting Log in to save

The DFT Lead Engineer joins the ASIC Product Division to lead comprehensive DFT programs from chip-level specification through implementation, verification, and production release. This role involves managing SoC activities including architecture, test insertion, pattern generation, coverage improvement, post-silicon debug, and yield optimization. The engineer will collaborate with Physical Design and STA teams for timing closure while interacting with external customers to meet specific feature requirements and DPPM goals. Key responsibilities include implementing Scan, MBIST, TAP, LBIST, IO, and SerDes integration, as well as automating test vector generation flows. Required technical skills include proficiency in Verilog, TCL, PERL, RUBY, PYTHON, or C++. The role requires expertise in tools like Mentor TestKompress, TetraMax, and Fastscan, alongside knowledge of IEEE1149.1, IEEE1149.6, IEE1687, IJTAG, ICL, and PDL to solve testability problems for 7nm and beyond.

Skills

DFT ATPG Scan Compression MBIST Tessent SSN Mentor TestKompress TetraMax Fastscan Verilog TCL Python C++ Perl Ruby STA IEEE1149.1 IEEE1149.6 IEE1687 IJTAG ICL PDL ATE

What you'll do

  • Define DFT specifications based on customer requirements and DPPM goals for ASIC products.
  • Implement Scan, MBIST, TAP, LBIST, IO, and SerDes features into the design.
  • Collaborate with STA and Physical Design teams to achieve DFT mode timing closure.
  • Generate, verify, and debug test vectors prior to tape release.
  • Validate and debug test vectors on ATE during the silicon bring-up phase.
  • Perform silicon failure analysis, diagnostics, and yield improvement activities.
  • Automate DFT and test vector generation flows using scripting languages like TCL or Python.
  • Develop innovative DFT solutions to solve testability problems for advanced process nodes.

What we're looking for

  • Bachelor's degree in Electrical/Electronic/Computer Engineering and 12+ years of relevant industry experience.
  • Master's degree in Electrical/Electronic/Computer Engineering and 10+ years of relevant industry experience.
  • Strong background in DFT, including IO and Analog DFT, ATPG, Scan, BIST, and scan compression.
  • Proficiency in Verilog coding, testbench generation, and simulation.
  • Ability to code using TCL, PERL, RUBY, PYTHON, C++, or similar languages.
  • Knowledge of IEEE1149.1, IEEE1149.6, IEE1687, IJTAG, ICL, and PDL.
  • Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification, and silicon debug (preferred).
  • Experience working on ATE or Tessent SSN (preferred).

Related searches

More DFT Lead Engineer jobs DFT Lead Engineer jobs in San Jose All jobs at Broadcom

More like this

Similar roles

ASIC DFT Engineer

Broadcom

San Jose, CA 17 days ago
DFT ATPG Scan Insertion MBIST TAP LBIST Verilog Tessent SSN Mentor TestKompress TetraMax Fastscan IEEE1149.1 IEEE1149.6 IEE1687 IJTAG ICL PDL STA SerDes DDR PCIe
10+ yrs exp
Save

CPU DFT Engineer

Qualcomm

Santa Clara, CA 43 days ago $142,200–$213,400
DFT ATPG Mentor Tessent Verilog VHDL TCL Python Shell Scripting Perl JTAG MBIST LBIST Scan Compression IEEE 1500 VLSI Test Pattern Translation
2+ yrs exp
Save

Senior DFT Engineer

Nvidia

Santa Clara, CA 23 days ago $196,000–$310,500
DFT IEEE1149.1 IEEE1500 SSN Scan Compression IOBIST Memory BIST ATE Python DDR HBM Failure Analysis LVP Photon Emission ebeam probing Advantest 93k
10+ yrs exp Hybrid
Save

DFT Architect

Amd

San Jose, CA 11 days ago $232,000–$348,000
DFT Scan MBIST ATPG Scan Compression Verilog Tessent Streaming Scan Network STA FPGA Firmware Post-Silicon Debug Oscilloscope Synthesis High-speed IO PHY Digital Communication
Save

Principal DFT Engineer

SpaceX

Irvine, CA 43 days ago $210,000–$340,000
DFT ASIC Siemens Tessent ATPG Scan Insertion BIST Verilog SystemVerilog RTL Python Perl Tcl UPF Formal Verification Gate Level Simulation SDF ATE DRC
10+ yrs exp
Save

Principal DFT Engineer

SpaceX

Palo Alto, CA 43 days ago $220,000–$355,000
DFT ASIC Siemens Tessent ATPG Scan Insertion BIST Verilog SystemVerilog RTL Python Perl Tcl UPF Formal Verification Gate Level Simulation SDF ATE
10+ yrs exp
Save