DFT Lead Engineer

Broadcom

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $143,800–$230,000 / yr
Employment: Full-time
Posted: 77 days ago
Freshness: Confirmed live today
Closes: Feb 7, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $202k

This role $187k

$131k $263k

below market most similar roles pay here above market

This role pays less than 60% of similar roles. Most pay $177,087–$227,300 — the blue band above. At the midpoint, this role pays about $187k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · DFT Lead Engineer

Role Posting Log in to save

The DFT Lead Engineer joins the ASIC Product Division to lead comprehensive DFT programs from chip-level specification through implementation and verification to production release. This role involves defining DFT specifications, performing test insertion, pattern generation, coverage improvement, and post-silicon debug to meet product test metrics. Key responsibilities include working with Physical Design and STA teams for timing closure, validating test vectors on ATE during silicon bring-up, and innovating solutions for 7nm and beyond. Candidates must utilize technologies such as TCL, PERL, RUBY, PYTHON, C++, Verilog, and Tessent SSN. Required expertise includes Scan, MBIST, TAP, LBIST, and IO integration, alongside knowledge of IEEE1149.1, IEEE1149.6, IEE1687, and IJTAG. The work addresses complex testability problems for high-performance semiconductor designs and customer-specific feature requirements.

Skills

DFT ATPG Scan Insertion MBIST TCL Python C++ Verilog Tessent SSN TetraMax Fastscan Mentor TestKompress IEEE1149.1 IEEE1149.6 IEE1687 IJTAG ICL PDL STA SerDes DDR PCIe ATE Ruby Perl

What you'll do

Define DFT specifications based on customer requirements and DPPM goals for ASIC designs.
Implement DFT features including Scan, MBIST, TAP, LBIST, IO, and SerDes integration.
Work with STA and DI engineers to achieve DFT mode timing closure.
Generate, verify, and debug test vectors before tape release and during silicon bring-up.
Perform silicon failure analysis, diagnostics, and yield improvement efforts.
Automate DFT and test vector generation flows using scripting languages like Python or Perl.
Innovate new DFT solutions to solve testability problems for 7nm and beyond processes.
Debug customer returned parts on ATE and provide technical support to global stakeholders.

What we're looking for

Bachelors in Electrical/Electronic/Computer Engineering and 12+ years of relevant industry experience.
Masters Degree in Electrical/Electronic/Computer Engineering and 10+ years of relevant industry experience.
Strong DFT background including IO and Analog DFT, ATPG, Scan, and BIST.
Experience in Scan Insertion, scan compression, and ATPG vector generation, simulation, and debugging.
Experience in Verilog coding, testbench generation, and simulation.
Experience with Memory BIST insertion and verification on embedded memory and Boundary scan.
Knowledge of IEEE1149.1, IEEE1149.6, IEE1687, IJTAG, ICL, and PDL.
Experience working on the ATE is a plus (preferred).
Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification and silicon debug is a plus (preferred).
Experience working on Tessent SSN is highly desired (preferred).

Similar roles

CPU DFT Engineer

Qualcomm

Santa Clara, CA 40 days ago $147,900–$221,900

DFT ASIC Design Verilog VHDL Mentor Tessent TCL Python Perl Shell Scripting JTAG ATPG Scan Compression MBIST LBIST IEEE 1500

2+ yrs exp

Save

CPU Core Staff DFT Engineer

Amd

Santa Clara, CA 46 days ago $200,000–$300,000

DFT ATPG Verilog Tessent JTAG MBIST LBIST Perl TCL Linux Scan Compression IEEE 1149.1 Silicon Bring-up ATE Agentic AI

Save

DFT Engineer

Broadcom

San Jose, CA 57 days ago $121,900–$195,000

DFT ATPG MBIST Tessent Scan IJTAG CMOS Semiconductor Manufacturing Lithography Etch Deposition CMP Implant Data Analytics Root Cause Analysis Failure Analysis Silicon Bring-Up Yield Enhancement

8+ yrs exp

Save

DFT Engineer

Amd

Austin, TX 74 days ago $139,680–$209,520

DFT DFD SystemVerilog Verilog SystemC C++ UVM Tessent JTAG LBIST MBIST Scan ATPG ICL/PDL Static Timing Analysis Perl Ruby Makefile Shell ATE post‑silicon bring‑up RTL ASIC Verification

Hybrid

Save

DFT Engineer

Broadcom

Austin, TX 63 days ago $109,700–$175,500

DFT MBIST Scan Insertion ATPG ATE Pattern Development Yield Analysis Silicon Debugging RTL Lint Checking Scan Compression Mentor Tessent Synopsys DFT Perl STA Constraint Development Digital Logic Simulation

8+ yrs exp

Save

DFT CAD Engineer

Apple Inc

Austin, TX 103 days ago

DFT ATPG Tcl Perl Python Verilog VHDL JTAG MBIST IEEE 1500 Scan Compression Logic Synthesis STA DRC Waveform Debugging Simulators

3+ yrs exp

Save