ASIC Design Engineer, SoC Interconnect, Cache & Memory Systems

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$101,400–$152,200 / yr
Posted
10 days ago
Freshness
Confirmed live 2 days ago
Closes
Apr 20, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $197k
This role $127k
$84k $262k
below market most similar roles pay here above market

This role pays less than 95% of similar roles. Most pay $165,975–$227,500 — the blue band above. At the midpoint, this role pays about $127k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 594 open roles on FindRole.

Listed pay typically runs $147,900–$219,400 across 568 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer, SoC Interconnect, Cache & Memory Systems

Role Posting Log in to save

The ASIC Design Engineer – SoC Interconnect, Cache & Memory Systems joins the ASICS Engineering group to contribute to the architecture, microarchitecture, design, and deployment of next-generation SoC solutions. The role involves developing microarchitecture definitions, designing and validating RTL for SoC interconnects, cache controllers, and DDR memory controllers, and optimizing designs for performance, power, area, and timing. Key responsibilities include collaborating with architects on hardware feasibility, supporting synthesis and physical design activities, and performing pre-silicon and post-silicon debugging. Candidates must possess skills in Verilog, SystemVerilog, C, C++, and Python, alongside knowledge of digital logic design and ASIC methodologies. The work focuses on solving complex hardware problems for high-performance subsystems, including on-chip communication fabrics, memory controllers, and low-power design methodologies for advanced silicon products.

What does a ASIC Design Engineer earn in California?

Median $214000 from 44 postings across 8 companies.

See salary data

Skills

ASIC Design SoC Design Verilog SystemVerilog RTL Design C C++ Python Computer Architecture DDR LPDDR Cache Controllers Synopsys Timing Closure Physical Design Power Analysis Gate-level Simulation Functional Verification Low-power Design ARM x86

What you'll do

  • Develop microarchitecture definitions and design specifications for complex SoC subsystems.
  • Design, implement, and validate RTL for interconnects, cache controllers, and memory subsystems.
  • Optimize designs for performance, power, area, timing, and scalability.
  • Develop test plans and review coverage with verification teams to achieve design quality goals.
  • Support synthesis, timing closure, power analysis, and gate-level simulations.
  • Investigate and resolve pre-silicon and post-silicon issues throughout the product development cycle.
  • Contribute to C/C++ modeling and design methodologies to enhance engineering productivity.

What we're looking for

  • Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 0-4+ years of industry experience or relevant academic experience in ASIC/SoC design.
  • Experience or coursework in Verilog and/or SystemVerilog RTL design, Computer Architecture, ASIC design methodologies, and Digital logic design.
  • Proficiency in C, C++, and/or Python programming.
  • Strong analytical, problem-solving, communication, and collaboration skills.
  • Experience in SoC interconnects, cache/memory subsystems, or DDR/LPDDR memory controller architecture (preferred).
  • Knowledge of ARM or x86 processor architectures and bus protocols (preferred).
  • Bachelor's degree in Science, Engineering, or related field.

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