ASIC Design Engineer
Quick summary
- Work type
- On-site
- Location
- Santa Clara, CA
- Salary
- $126,800–$190,900 / yr
- Posted
- 21 days ago
Market check
Salary context
How this pay compares to similar roles
This role pays less than 79% of similar roles. Most pay $165,250–$216,250 — the shaded band above. At the midpoint, this role pays about $159k versus about $191k for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has 969 open roles on FindRole.
Listed pay typically runs $163,300–$272,100 across 756 roles with salary data.
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At a glance
TL;DR · ASIC Design Engineer
Join our dynamic ASIC design team as an experienced engineer where you will play a pivotal role in shaping the next generation of Apple’s innovative products. You will engage in cutting-edge architecture research and development, focusing on memory subsystems and highly interconnected system architectures. Your daily tasks include working with RTL/micro-architecture, designing high-performance memory controllers and PHYs, and implementing DFI interfaces along with calibration/training mechanisms for DRAM. Additionally, you will collaborate closely with the performance team to develop simulators and test suites that ensure optimal power consumption and area efficiency in system-on-a-chip (SoC) designs. This role demands expertise in high-performance memory subsystems and a deep understanding of complex SoCs, making it ideal for those passionate about pushing hardware technology boundaries.
Skills
What you'll do
- Conduct architecture research for memory or highly interconnected system designs.
- Develop RTL/micro-architecture for ASIC design projects.
- Design high-performance memory subsystems including DRAM controllers and PHY architectures.
- Implement DFI interfaces and develop calibration/training mechanisms for DRAM systems.
- Collaborate with performance teams to create simulators, models, and test suites.
What we're looking for
- Experience in ASIC design, including architecture research and development.
- Proficiency in RTL/micro-architecture and high-performance memory subsystems.
- Knowledge of DRAM controller, PHY architecture, DFI interface, and calibration/training mechanisms.
- Systems experience in characterizing performance, conducting comparison studies, and documenting results.
- Ability to drive new memory system architectures from DRAM up.
- Expertise in developing memory hierarchies for high-performance parallel computer architectures.
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