ASIC Design Engineer

Apple Inc

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$129,300–$194,700 / yr
Posted
164 days ago
Freshness
Confirmed live today

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $196k
This role $162k
$117k $242k
below market most similar roles pay here above market

This role pays less than 76% of similar roles. Most pay $167,900–$224,075 — the blue band above. At the midpoint, this role pays about $162k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · ASIC Design Engineer

JOB TITLE: ASIC Design Engineer As an ASIC Design Engineer, you will join a complex hardware team focused on crafting upcoming products and transforming hardware technology. Your primary responsibilities include architecture research and development for memory or highly interconnected system architectures, specifically focusing on RTL and micro-architecture. You will drive new memory system architectures from DRAM up, exploring trade-offs in system performance, area, and power consumption. The role involves developing memory hierarchies for high-performance parallel computer architectures and system-on-a-chip designs. You will also work with the performance team to develop simulators, models, and test suites. Key technical requirements include knowledge of high-performance memory subsystems, including DRAM controllers, PHY architecture, DFI interfaces, and calibration algorithms, while performing performance characterization and comparison studies.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

What you'll do

  • Research and develop memory or highly interconnected system architectures.
  • Design RTL and micro-architecture for ASIC components.
  • Design and develop high-performance memory subsystems including DRAM controllers and PHYs.
  • Implement DFI interfaces and DRAM interface calibration/training mechanisms.
  • Characterize system performance and conduct comparative studies.
  • Document and publish technical results from performance characterizations.
  • Explore architecture trade-offs regarding system performance, area, and power consumption.
  • Develop performance/power simulators, models, and test suites.

What we're looking for

  • Experience in ASIC design with RTL or micro-architecture.
  • Experience in architecture research and/or development of memory or highly interconnected system architectures.
  • Systems experience in characterizing performance, doing comparison studies, and documenting and publishing results.
  • Knowledge of high-performance memory subsystems, including dram controller, PHY architecture, DFI interface, and calibration mechanisms (preferred).
  • Drive new memory system architectures from DRAM up (preferred).
  • Explore architecture and feature trade-offs in system performance, area, and power consumption (preferred).
  • Develop memory hierarchies for high performance parallel computer architectures (SoC) (preferred).
  • Bachelor's Degree.

More like this

Similar roles

ASIC Design Engineer

Apple Inc

Santa Clara, CA 40 days ago $129,300–$194,700
ASIC Design RTL Micro-architecture SoC DRAM DFI PHY Memory Subsystem Simulators System-on-a-Chip Architecture Research

ASIC Design Engineer

Apple Inc

Cupertino, CA 83 days ago $184,700–$324,800
ASIC Design SoC Design Logic Design Lint CDC Synthesis ECO STA Physical Design Power Management Clock Management Python Perl TCL Microarchitecture IP Integration
10+ yrs exp

ASIC Design Engineer

Apple Inc

Cupertino, CA 83 days ago $150,400–$277,600
ASIC Design SoC Design Logic Design Lint CDC Synthesis ECO STA Physical Design Power Management Clock Management Python Perl TCL Microarchitecture IP Integration
3+ yrs exp

ASIC Design and Integration Engineer

Apple Inc

Cupertino, CA 78 days ago $129,300–$194,700
SystemVerilog RTL Design ASIC Design Synthesis Formal Verification Simulation Timing Analysis Power Optimization CDC RDC Micro-architecture PPA

ASIC Design and Integration Engineer

Apple Inc

Cupertino, CA 40 days ago $150,400–$277,600
SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Formal Verification FPGA Prototyping PCIe CDC RDC LINT LEC Power Optimization Low-Power Design
3+ yrs exp

ASIC Design and Integration Engineer

Apple Inc

Cupertino, CA 7 days ago $184,700–$324,800
Verilog RTL ASIC Design SOC Design CDC Lint Synthesis ECO Python Perl Tcl STA Physical Design GenAI System Architecture
10+ yrs exp