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FPGA Vivado Digital Signal Processing C C++ Linux DSP Algorithms RTL Development Timing Closure Resource Optimization System-Level Software integration code Epiq Solution PDK +8 more Show less

Python COTS EVMS MBSE Kubernetes AWS Terraform Git JIRA Confluence CI/CD PostgreSQL Mentoring Risk Management Communication Skills +10 more Show less

Mentor_Graphics schematic PCB_layout MathCad PSpice Saber Ethernet PCIe SerDes eFuse FET Thermal LiB DC_DC FMEA Preliminary_Hazard_Analyses embedded_software verification_and_validation high_speed_Communication_Buses Body_controls lighting_controls +16 more Show less

LTspice Spice TI WorkBench Cadence Allegro DxDesigner AC Power Integrity Simulation DC Power Integrity Simulation High efficiency DC-DC power conversion Phase and gain margins Power supply layout Thermal design rules Multi-phase power delivery Ultra-low noise power delivery Power-up sequencing PCB layout techniques Grounding techniques Low noise etch techniques Technical presentation skills +13 more Show less

Verilog VHDL Python Tcl PCIe I2C SPI MDC/MDIO Ethernet Gigabit Ethernet Multi-Gigabit Ethernet 10 Gigabit Ethernet 25G Ethernet 100G Ethernet 400G Ethernet 800G Ethernet DRAM CPU PCB设计 硬件调试 系统级测试 软件团队合作 自动机能力 团队协作 沟通技巧 +20 more Show less

Siemens_NX AutoCAD SAP Teamcenter GD&T Microsoft_Office_365 Adobe_Acrobat PLM CoPilot Teams +5 more Show less

IEC 60601 Electronic PCB design Schematics Circuit simulation PCB Assembly Drawings Design Controls Risk Management Change Control Quality Engineering CI/CD Statistical Analysis Python PostgreSQL Git JIRA Confluence +11 more Show less

Python Perl Verilog SystemVerilog dc_shell VCS Debussy GDB Kubernetes Terraform CI/CD Git Unix/Linux +8 more Show less

Mentor_Graphics PCB_layout_design High_speed_Communication_Buses Ethernet PCIe SerDes Design_rule_checks Design_for_Manufacturability ECAD_library_parts Digital_analog_HW_interfaces Mentor_Graphics_schematic_and_layout Simulation_tools Component_engineering Procurement Supply_chain_teams Design_for_Assembly SI_PI_EMC_Thermal_Mechanical_expertise +12 more Show less

Mentor_Graphics_Xpedition Mentor_Graphics_ORCAD PCB_layout Circuit_design Schematic_creation Oscilloscopes Signal_generators Multimeters Power_supplies Automotive_software_architecture Automotive_electronic_hardware Semiconductor_design Electrical_Engineering Electronic_control_unit CI/CD +10 more Show less

JIRA Confluence SharePoint Agile PCIe BMC BIOS Redfish Python C++ Linux Networking Thermal Management Mechanical Engineering Server Technologies SIP PI Kubernetes Git +14 more Show less

SystemVerilog UVM Python Perl C++ VHDL Verilog SystemC AI ML GenAI 4G/5G 3GPP Formal verification Simulation acceleration Unix/Linux Makefiles XML OOP HW/SW co-verification +15 more Show less

Allegro PCB Editor Allegro Package Designer Design Entry HDL LTspice TI WorkBench Spice PCB design rules Stackup and constraint management Power supply layout Thermal design rules High-speed PCB design DC-DFM VNA TDR Oscilloscope Logic analyzer +11 more Show less

SiemensNX PLM EarnedValueManagement ASMEY14x CAD PDP CI/CD Kubernetes AWS GitLab Jira Confluence Python PostgreSQL Terraform Docker Prometheus Grafana +13 more Show less

OrCAD Cadence Allegro PCIe DDR Ethernet SerDes SIPI PDN EMI Python TCL Perl Oscilloscopes Logic analyzers Protocol analyzers High-speed design High-power design MULTILAYER PCBs Cross-functional collaboration Technical documentation +15 more Show less

Synopsys_DC DCG FC Primetime Verilog SystemVerilog TCL Shell Perl SDC STA Clocking Timing_Exceptions Async_Boundaries HDL Digital_Design_Concepts +11 more Show less

verilog system-verilog RTL DFT AHB AXI ASIC SoC Security Crypto Cryptography Encryption side-channel High-speed Low Area Low Power Root of Trust RNG symmetric crypto asymmetric crypto silicon test bus protocols clocks/resets debug concepts +19 more Show less

Cadence VLSI ASIC SerDes PLL Analog to Digital converters ESD structures CMOS Sub-micron CMOS technologies +4 more Show less

Python C C++ Verilog System Verilog Unix/Linux Shell scripting Makefiles XML RTL coding Synthesis Clock domain crossing Low power design Verification +9 more Show less

Cadence CMOS PLL SerDes Analog to Digital converters ESD structures +1 more Show less