Senior Mask Design Engineer - Hardware

Nvidia

Remote

Quick summary

Work type: Remote
Location: Santa Clara, CA
Salary: $132,000–$207,000 / yr
Posted: 51 days ago

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Competitive pay

How this pay compares to similar roles

Similar $180k

This role $170k

$123k most similar roles pay here $220k

This role pays less than 65% of similar roles. Most pay $155,425–$205,000 — the shaded band above. At the midpoint, this role pays about $170k versus about $180k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Senior Mask Design Engineer - Hardware

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As a senior Mask Layout Design Engineer on our cutting-edge semiconductor team, you will be responsible for creating physical layouts for complex mixed-signal functions such as PLLs, high-speed SerDes, and analog-to-digital converters using Cadence tools. Your daily tasks will involve designing ESD structures and implementing these designs in groundbreaking sub-micron CMOS technologies. This role requires a minimum of seven years of proven experience in mask layout design, along with expertise in semiconductor fabrication processes and an understanding of the intricacies involved in mixed-signal circuitry. You must be proficient in using Cadence tools and have a strong background in physical design methodologies to ensure high-performance and reliable chip designs at scale.

Skills

Cadence CMOS PLL SerDes Analog to Digital converters ESD structures

What you'll do

Perform physical layout for mixed-signal functions such as PLLs, high-speed SerDes, and ADCs.
Design ESD structures using cutting-edge sub-micron CMOS technologies.
Utilize Cadence tools for mask layout design in advanced semiconductor processes.
Ensure compliance with design rules and manufacturing constraints throughout the layout process.
Optimize layouts for performance, power consumption, and area efficiency.