Senior Hardware/Software Design Engineer

Leidos

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Annapolis Junction, MD
Salary: $131,300–$237,350 / yr
Posted: 53 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $188k

This role $184k

$119k most similar roles pay here $250k

This role pays more than 53% of similar roles. Most pay $162,150–$214,000 — the shaded band above. At the midpoint, this role pays about $184k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Leidos

Leidos is an industry and technology leader serving government and commercial customers with smarter, more efficient digital and mission innovations.

Leidos currently has 264 open roles on FindRole.

Listed pay typically runs $92,300–$166,850 across 245 roles with salary data.

Most-posted roles

View all roles at Leidos

At a glance

TL;DR · Senior Hardware/Software Design Engineer

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Senior Hardware/Software Design Engineer (HSDE-3) joins the Cyber & Analytics Business Area to support a signals analysis organization through rapid prototyping and advanced technology research. Working within a small team, the engineer designs, develops, constructs, and tests electronic hardware and software processing components for subsystems supporting RF communication and collection systems. Key responsibilities include leading technical design efforts, implementing digital signal processing algorithms in FPGA hardware, ensuring timing closure and resource optimization, and integrating these components with existing Linux code bases to bridge the gap between FPGA and the software stack. The role requires proficiency in FPGA coding, C, C++, and Vivado, along with knowledge of Linux OS and DSP theory. This position addresses critical mission requirements by developing integrated solutions for signal processing blocks within a high-paced technical environment focused on intelligence data.

Skills

FPGA Digital Signal Processing C C++ Vivado Linux RTL Hardware Design RF Communication Epiq Solution PDK Timing Closure Resource Optimization

What you'll do

Design, develop, construct, and test electronic hardware components for RF communication and collection systems.
Implement digital signal processing (DSP) algorithms and associated technical components in FPGA hardware.
Perform FPGA RTL development including timing closure and resource optimization.
Integrate FPGA code with existing Linux code bases and software stacks.
Develop system-level integration code using C and C++.
Lead technical design efforts for mission-critical subsystems.
Document all hardware and software engineering efforts and designs.

What we're looking for

Candidates must possess a Bachelor's degree.
Candidates must have at least 8 years of relevant experience.
Candidates must possess an active TS/SCI security clearance with Polygraph.
Candidates must have strong experience in FPGA coding and Digital Signal Processing theory and application.
Candidates must be proficient in C and C++ programming languages.
Candidates must have experience interfacing FPGA code with existing code bases and software.
Experience with Vivado is required.
Experience with Epiq Solution PDK is preferred.

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