Senior Mask Design Engineer - Hardware

Nvidia

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $132,000–$207,000 / yr
Posted: 32 days ago

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Competitive pay

How this pay compares to similar roles

Similar $180k

This role $170k

$123k most similar roles pay here $220k

This role pays less than 65% of similar roles. Most pay $155,425–$205,000 — the shaded band above. At the midpoint, this role pays about $170k versus about $180k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Senior Mask Design Engineer - Hardware

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We are seeking a Senior Mask Layout Design Engineer to join our dynamic team, responsible for developing high-speed mixed-signal circuits. In this role, you will perform physical layout for complex functions such as PLLs, SerDes, and ADCs in advanced sub-micron CMOS technologies using Cadence tools. You will collaborate closely with ASIC and mixed-signal engineers to tailor designs for integration into VLSI products. The ideal candidate holds a BSEE or equivalent experience and has at least 8 years of industry expertise, along with extensive proficiency in Cadence custom circuit design tools. This position involves working on cutting-edge semiconductor technologies that drive innovative product development at scale.

Skills

Cadence VLSI ASIC SerDes PLL Analog to Digital converters ESD structures CMOS Sub-micron CMOS technologies

What you'll do

Perform physical layout for mixed-signal functions like PLLs, high-speed SerDes, and ADCs in sub-micron CMOS technologies.
Customize designs for integration in VLSI products working with ASIC engineers.
Utilize Cadence custom circuit design tools proficiently for mask layout creation.
Ensure compliance with innovative sub-micron CMOS technology standards during layout.
Collaborate on the physical implementation of ESD structures within mixed-signal circuits.