Senior Mask Design Engineer, Hardware

Nvidia

Confirmed live 3 days ago Trusted

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $132,000–$207,000 / yr
Posted: 131 days ago
Freshness: Confirmed live 3 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $192k

This role $170k

$122k most similar roles pay here $229k

This role pays less than 74% of similar roles. Most pay $169,250–$214,000 — the shaded band above. At the midpoint, this role pays about $170k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior Mask Design Engineer, Hardware

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As a Senior Mask Design Engineer - Hardware, you will join a multifaceted team responsible for high-speed mixed-signal circuit designs. You will perform physical layout for critical functions including PLLs, high-speed SerDes, Analog to Digital converters, and ESD structures using innovative sub-micron CMOS technologies. Working in a multi-functional capacity with ASIC and mixed-signal engineers, you will customize designs for integration into VLSI products while participating in floor planning, custom layout, and verification against design rules and schematics. The role requires expertise in Cadence custom circuit design tools and experience with verification tools like Dracula, Hercules, Calibre, and Primeyield. You must possess a deep understanding of analog circuit layout concepts and proficiency in scripting languages such as Perl, Python, and Skill to manage DRC and LVS checking flows while customizing decks for production.

Skills

Cadence Mixed-Signal CMOS VLSI DRC LVS Python Perl SKILL Calibre Dracula Hercules Primeyield Floor Planning SerDes PLL

What you'll do

Perform physical layout for mixed-signal functions like PLLs, high-speed SerDes, and ADC structures.
Design layouts using innovative sub-micron CMOS technologies with Cadence tools.
Execute floor planning and custom layout designs for VLSI products.
Verify designs against specific design rules and schematics.
Run and debug designs using verification tools like Dracula, Hercules, Calibre, and Primeyield.
Customize DRC and LVS checking decks.
Develop scripts using Perl, Python, or SKILL to automate design processes.

What we're looking for

Bachelor of Science in Electrical Engineering (BSEE) or equivalent experience.
Minimum of 8 years of industry experience.
Deep understanding of analog circuit layout concepts in submicron CMOS technologies.
Authority with Cadence custom circuit design tools.
Experience running and debugging with verification tools such as Dracula, Hercules, Calibre, and Primeyield.
Knowledge of DRC and LVS checking flows and the ability to customize decks.
Proficiency in scripting languages including Perl, Python, and SKILL.

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