Browse tech roles

Static Timing Analysis STA Synthesis ECO RTL Floor-planning DFT Python Tcl Make Synopsys PrimeTime Cadence Tempus Physical Design +8 more Show less

STA PrimeTime Tempus ICC2 Innovus TCL Python Perl RTL GDS Spice Signal Integrity Layout Parasitic Extraction ASIC Back-end Design CTS POCV AOCV +12 more Show less

Static Timing Analysis PrimeTime StarRC PrimeClosure Tempus Tcl Python Perl ASIC Design Flow Clock Tree Synthesis UPF POCV Multi-Corner Analysis Formal Equivalency Check +9 more Show less

Static Timing Analysis (STA) Timing Closure Physical Design Logic Synthesis DFT Noise Analysis RTL ASIC AMS Equivalence Checking Automation +6 more Show less

STA PrimeTime Tempus TCL Python Perl ICC2 Innovus RTL GDS Spice Signal Integrity Layout Parasitic Extraction Physical Design Timing Closure +10 more Show less

STA Primetime Fishtail TCM Tcl Perl Python ASIC Design Timing Closure Power Analysis RTL Design Physical Design Multi-voltage Domain Crossing Clock Domain Crossing Synthesis +10 more Show less

DTCO STA Hspice Finesim PrimeSim AFS Spectre PT Tempus Genus Innovus Python Perl TCL Unix Shell C/C++ RTL to GDS PPA Analysis +13 more Show less

Static Timing Analysis STA ASIC Physical Design Synthesis Floor-planning CTS Routing Equivalence Checking Timing Constraints Power Convergence ECO AI LLM +9 more Show less

Physical Design Static Timing Analysis Logic Synthesis Floorplanning Clock-tree Synthesis Routing ECO RTL Python Tcl Perl Make AI Deep Learning LLMs EDA Tools +11 more Show less

STA Timing Closure Physical Design RTL Synthesis DFT Clocking TCL Python Perl Shell Scripting EDA Tools VLSI ECO CMOS Digital Logic Design +11 more Show less

STA Timing Closure Physical Design TCL Python Perl Shell Scripting EDA Tools DFT Synthesis ECO Tapeout RTL Clocking OCV +10 more Show less

STA Timing Closure TCL Python Perl Shell Scripting EDA Tools DFT RTL Synthesis ECO PPA post silicon debug Tapeout OCV Cross-talk Clocking +12 more Show less

Physical Design Sign-off FPGA Python Perl Tcl Power Integrity CAD +3 more Show less

STA PrimeTime Tempus ICC2 Innovus TCL Python Perl RTL GDS Spice Signal Integrity Layout Parasitic Extraction Timing Closure CTS POCV AOCV +12 more Show less

PTP NTP TWSTFT GNSS RF Optical Links Python SQL Tableau MATLAB R Kalman Filtering FPGA Agile Excel +10 more Show less

STA Spice Simulation Python TCL CAD Development GenAI ASIC Design Cell Characterization Signoff Timing +4 more Show less

STA Primetime SDC Tcl Perl ASIC Design Timing Closure Synthesis DFT RTL Signal Integrity Physical Design SoC Design +8 more Show less

STA Primetime SDC Tcl Perl ASIC Design Timing Closure Synthesis DFT RTL Signal Integrity SoC Design +7 more Show less

STA Primetime SDC Tcl Perl ASIC Design Timing Closure Synthesis DFT RTL Signal Integrity SoC Design +7 more Show less

STA Primetime SDC Tcl Perl ASIC Design Synthesis DFT Timing Closure RTL Signal Integrity Physical Design SoC Design +8 more Show less