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Static Timing Analysis Timing Constraints Generation ECOs Physical Design Optimization Synthesis Placement Routing Logic Restructuring STA Tools Deep Sub-Micron Process Nodes GPU STA CPU STA LPD STA SOC STA Logic Synthesis Equivalence Checking DFT Logic AMS Designs Methodology Development Flow Development Automation +16 more Show less

Python Tcl Make Synopsys_PrimeTime Cadence_Tempus EDA_tools Static_Timing_Analysis Timing_Constraints_Generation ECOs Physical_Design_Optimization Logic_Synthesis Logical_Equivalence_Checking DFT_logic Deep_Sub_Micron_Technology Process_Variations_Modeling Methodology_Development_Automation +11 more Show less

Tcl Python Perl Cadence Synopsys ASIC STA SDC On-Chip_Variation Signal_Integrity IR-drop_aware_STA MMMC_Analysis ECOs RTL Physical_Design DFT Power_Performance_Area_Tradeoffs EDA_Tools +13 more Show less

Verilog SystemC VHDL Cadence Synopsys Tensilica Mentor Graphics ModelSim Python Git JIRA Confluence CI/CD +8 more Show less

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TCL Perl Python Verilog SystemVerilog Timing_Corner_Analysis UPF DFT BIST Static_Timing_Analysis Place_and_Route Floor_Planning CTS Routing Signal_Integrity Logic_Equivalence_Checking Physical_Design Synthesis ASIC_Design_Flow +14 more Show less

TCL Perl Python Verilog SystemVerilog UPF DFT BIST Static_Timing_Analysis Logic_Equivalence Physical_Design Synthesis SDC Place_and_Route Floor_Planning CTS Routing Signal_Integrity Low_Power_Design +14 more Show less

TCL Perl Python Prime-time Tempus ICC2 Innovus STA AOCV POCV CTS ASIC Cross-talk noise Signal Integrity Layout Parasitic Extraction +10 more Show less