Senior ASIC Timing Engineer

Nvidia

Confirmed live 2 days ago High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAAustin, TXHillsboro, ORDurham, NC
Salary: $136,000–$218,500 / yr
Posted: 32 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $194k

This role $177k

$126k most similar roles pay here $232k

This role pays less than 56% of similar roles. Most pay $172,000–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior ASIC Timing Engineer

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As a Senior ASIC Timing Engineer, you will join a dynamic team to drive timing analysis and closure for GPUs, CPUs, LPUs, and SoCs at the block, cluster, and full chip levels. You will collaborate with cross-functional teams including RTL, DFX, and Clocks to develop timing closure strategies, create constraints, and manage power convergence while implementing ECOs. The role involves improving timing convergence flows in partnership with methodology teams. Required expertise includes hands-on experience in full-chip and sub-chip Static Timing Analysis (STA), crosstalk and noise analysis, and physical design optimization such as synthesis, placement, routing, and logic restructuring. You will work with industry standard STA tools on deep sub-micron process nodes. The role focuses on solving complex timing challenges within high-performance computing hardware components like GPUs and SoCs.

Skills

Static Timing Analysis (STA) Timing Closure Physical Design Logic Synthesis DFT Noise Analysis RTL ASIC AMS Equivalence Checking Automation

What you'll do

Lead timing analysis and closure processes for GPUs, CPUs, LPUs, and SoCs at block, cluster, and full chip levels.
Develop timing constraints and drive timing and power convergence in collaboration with cross-functional teams.
Implement Engineering Change Orders (ECOs) to fix timing paths including crosstalk and noise issues.
Improve timing convergence flows by collaborating with methodology teams.
Manage and generate timing constraints for complex integrated circuits.
Perform physical design optimizations such as synthesis, placement, routing, and logic restructuring to improve performance.
Model and converge timing for designs on deep sub-micron process nodes.
Develop automation and tools for STA and timing convergence workflows.

What we're looking for

BS in Electrical or Computer Engineering with 5 years of experience is required.
MS in Electrical or Computer Engineering with 3 years of experience is required.
Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence is required.
Experience in generating and managing timing constraints is required.
Expertise in analyzing and fixing timing paths through ECOs, including crosstalk and noise analysis, is required.
Experience in physical design and optimization such as synthesis, placement, routing, and logic restructuring is required.
In-depth knowledge of industry standard STA and timing convergence tools is required.
Knowledge of deep sub-micron process nodes and experience modeling/converging timing in these nodes is required.

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