Senior ASIC Timing Engineer

Nvidia

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA · Austin, TX · Hillsboro, OR · Durham, NC
Salary: $136,000–$218,500 / yr
Posted: 3 days ago

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Competitive pay

How this pay compares to similar roles

Similar $190k

This role $177k

$126k most similar roles pay here $231k

This role pays more than 51% of similar roles. Most pay $163,416–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $190k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Senior ASIC Timing Engineer

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Join our dynamic team as an ASIC Timing Engineer where you will drive the timing analysis and closure processes for NVIDIA’s GPUs, CPUs, LPUs, and SoCs at various levels. Collaborate with cross-functional teams to develop timing strategies, create constraints, and implement ECOs to ensure timing and power convergence. Contribute to cutting-edge projects by improving timing flows in collaboration with methodology teams. Ideal candidates have a BS/MS in Electrical or Computer Engineering with 3-5 years of experience in STA and timing closure, hands-on expertise in full-chip/sub-chip Static Timing Analysis (STA), and deep knowledge of industry-standard tools for timing convergence at advanced process nodes. Experience in physical design optimization, logic synthesis, equivalence checking, DFT timing closure, and AMS designs is a plus.

Skills

Static Timing Analysis Timing Constraints Generation ECOs Physical Design Optimization Synthesis Placement Routing Logic Restructuring STA Tools Deep Sub-Micron Process Nodes GPU STA CPU STA LPD STA SOC STA Logic Synthesis Equivalence Checking DFT Logic AMS Designs Methodology Development Flow Development Automation

What you'll do

Lead the timing analysis and closure processes at block, cluster, and full chip levels for GPUs, CPUs, LPUs, and SoCs.
Devise timing closure strategies and create constraints to drive convergence with RTL, DFX, Clocks teams.
Implement ECOs to fix timing paths, including crosstalk and noise analysis, to improve design quality.
Optimize physical designs through synthesis, placement, routing, and logic restructuring for better timing and power.
Utilize industry-standard STA tools to model and converge timing in deep sub-micron process nodes.

What we're looking for

5+ years of experience in ASIC timing analysis and STA with a BS or 3+ years with an MS.
Proficient in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence.
Expertise in generating and managing timing constraints, fixing timing paths through ECOs.
Experience in physical design optimization including synthesis, placement, routing, and logic restructuring.
In-depth knowledge of industry-standard STA tools and deep sub-micron process nodes.
Background in domain-specific STA for GPUs, CPUs, LPUs, or SoCs.

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