Senior ASIC Timing Engineer

Nvidia

Confirmed live today Trusted

Hybrid

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Work type: Hybrid
Location: Santa Clara, CAAustin, TXHillsboro, ORDurham, NC
Employment: Full-time
Posted: 28 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior ASIC Timing Engineer

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The Senior ASIC Timing Engineer joins a dynamic team to drive timing analysis and closure for GPUs, CPUs, LPUs, and SoCs at the block, cluster, and full chip levels. The role involves collaborating with RTL, DFX, and Clocks teams to devise closure strategies, create timing constraints, drive power convergence, and implement ECOs. Key responsibilities include improving timing convergence flows and managing full-chip Static Timing Analysis. Candidates must possess expertise in industry standard STA tools, crosstalk and noise analysis, and physical design optimization including synthesis, placement, routing, and logic restructuring. The position requires experience with deep sub-micron process nodes and domain-specific knowledge of timing convergence for complex processors. This role addresses the technical challenges of timing and power convergence in high-performance computing hardware.

Skills

Static Timing Analysis (STA) Timing Closure Physical Design Logic Synthesis DFT RTL Noise Analysis Placement Routing Equivalence Checking AMS GPU LPU

What you'll do

Lead timing analysis and closure processes for GPUs, CPUs, LPUs, and SoCs at block, cluster, and full chip levels.
Create and manage timing constraints for complex integrated circuits.
Drive timing and power convergence in coordination with RTL, DFX, and Clocks teams.
Implement Engineering Change Orders (ECOs) to fix timing paths, crosstalk, and noise issues.
Improve timing convergence flows in collaboration with methodology teams.
Perform physical design optimizations including synthesis, placement, routing, and logic restructuring.
Model and converge timing for deep sub-micron process nodes.
Develop automation and methodologies for Static Timing Analysis (STA) flows.

What we're looking for

BS in Electrical or Computer Engineering with 5 years of experience or MS with 3 years of experience in Timing and STA.
Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing convergence, and timing constraints generation and management.
Expertise in analysis and fixing of timing paths through ECOs, including crosstalk and noise analysis.
Experience in physical design and optimization including synthesis, placement, routing, and logic restructuring to improve timing and power.
Expertise and in-depth knowledge of industry standard STA and timing convergence tools.
Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes.
Background in domain specific STA and timing convergence such as GPUs, CPUs, LPU or SOCs (preferred).
Background in logic synthesis, equivalence checking/FV, DFT logic, AMS designs, or methodology and flow development (preferred).

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