Timing Design Engineer

Apple Inc

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$120,300–$210,100 / yr
Posted
45 days ago

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $181k
This role $165k
$109k most similar roles pay here $230k

This role pays less than 68% of similar roles. Most pay $152,875–$209,750 — the shaded band above. At the midpoint, this role pays about $165k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 638 open roles on FindRole.

Listed pay typically runs $171,600–$272,100 across 505 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Timing Design Engineer

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As a Timing Design Engineer at our leading-edge semiconductor company, you will join the high-performance computing team as a mid-level professional. Your primary responsibilities include designing and optimizing timing closure for complex digital circuits to ensure reliable chip performance. You will work closely with layout designers and verification engineers to identify and resolve timing issues, ensuring that designs meet stringent performance targets. The role requires expertise in industry-standard tools like Cadence Genus and Synopsys IC Compiler, as well as a strong foundation in Verilog or SystemVerilog for circuit description. Additionally, you should have experience with scripting languages such as Python or Perl to automate design tasks. This position involves tackling challenging timing issues on large-scale integrated circuits used in high-performance computing applications, where precision and efficiency are critical.

Skills

Verilog SystemC VHDL Cadence Synopsys Tensilica Mentor Graphics ModelSim Python Git JIRA Confluence CI/CD

What you'll do

  • Develop and optimize timing constraints for complex digital designs.
  • Analyze post-layout simulation results to identify and resolve timing violations.
  • Collaborate on the creation of testbenches for verifying timing requirements.
  • Implement strategies to improve design performance without compromising power consumption.
  • Document detailed reports on timing analysis findings and recommendations.

What we're looking for

  • Bachelor’s degree in Electrical Engineering or related field required.
  • Proven experience in timing analysis and design for high-speed digital circuits.
  • Strong understanding of clock distribution, skew minimization techniques.
  • Experience with industry-standard EDA tools for timing closure.
  • Knowledge of scripting languages (Python, Perl) for automation tasks.
  • Familiarity with CMOS process technologies and their impact on timing.

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