Senior ASIC Timing Engineer

Nvidia

Quick summary

Work type
On-site
Location
Westford, MA · Durham, NC
Salary
$168,000–$264,500 / yr
Posted
8 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $190k
This role $216k
$127k most similar roles pay here $279k

This role pays more than 77% of similar roles. Most pay $162,873–$216,250 — the shaded band above. At the midpoint, this role pays about $216k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Senior ASIC Timing Engineer

Apply Now Log in to save

NVIDIA seeks a Senior ASIC Timing Design Engineer to join its elite Networking Silicon engineering team, focusing on developing cutting-edge high-speed communication devices. In this role, you will drive physical design and timing for high-frequency and low-power DPUs and SoCs at various levels, from block to full chip, optimizing performance, power, and area targets through synthesis parameters and constraints analysis. You will also support frontend and backend implementation tasks including equivalence checking, floor-planning, and ECO implementation. Ideal candidates have extensive experience in Static Timing Analysis (STA), timing constraint management, and physical design optimization using industry-standard EDA tools like Synopsys PrimeTime or Cadence Tempus, along with proficiency in Python, Tcl, and Make for automation. Additionally, a background in CPUs, GPUs, network processors, or SOC implementation is preferred, as well as knowledge of deep sub-micron technology effects and DFT timing closure techniques.

Skills

Python Tcl Make Synopsys_PrimeTime Cadence_Tempus EDA_tools Static_Timing_Analysis Timing_Constraints_Generation ECOs Physical_Design_Optimization Logic_Synthesis Logical_Equivalence_Checking DFT_logic Deep_Sub_Micron_Technology Process_Variations_Modeling Methodology_Development_Automation

What you'll do

  • Drive physical design and timing for high-frequency and low-power DPUs and SoCs at various levels.
  • Analyze and optimize synthesis parameters to meet performance, power, and area targets.
  • Implement frontend and backend processes from RTL to GDS2, including equivalence checking and ECOs.
  • Conduct static timing analysis (STA) and manage timing constraints for full-chip/sub-chip designs.
  • Optimize physical design through placement, routing, cell sizing, buffering, and logic restructuring.
  • Develop expertise in industry-standard EDA tools like Synopsys PrimeTime or Cadence Tempus.

What we're looking for

  • BS/MS in Electrical or Computer Engineering with 4+ years of relevant experience.
  • Expertise in full-chip/sub-chip Static Timing Analysis (STA) and timing constraints management.
  • Hands-on experience in physical design optimization, including placement, routing, and ECO implementation.
  • Proficiency in logic synthesis, equivalence checking, and DFT timing closure for various modes.
  • In-depth knowledge of industry-standard EDA tools like Synopsys PrimeTime or Cadence Tempus.

Related searches

More Senior ASIC Timing Engineer jobs Senior ASIC Timing Engineer jobs in Westford All jobs at Nvidia

More like this

Similar roles

Senior ASIC Timing Engineer

Nvidia

Santa Clara, CA 3 days ago $136,000–$218,500
Static Timing Analysis Timing Constraints Generation ECOs Physical Design Optimization Synthesis Placement Routing Logic Restructuring STA Tools Deep Sub-Micron Process Nodes GPU STA CPU STA LPD STA SOC STA Logic Synthesis Equivalence Checking DFT Logic AMS Designs Methodology Development Flow Development Automation
Hybrid
Save

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 80 days ago $136,000–$218,500
Verilog SystemVerilog Perl Python VCS Verdi GDB Random Stimulus Functional Coverage Assertion-Based Verification Logic Synthesis Timing Analysis Embedded Processors
Save

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 17 days ago $168,000–$264,500
Verilog System-Verilog RTL ASIC Logic Design Computer Architecture Digital Systems Timing Analysis ECO Post Silicon Debug Arbiters Scheduling Synchronization Bus Protocols Interconnect Networks Switches Virtual Channels
Save

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 88 days ago $168,000–$264,500
Verilog RTL C C++ Python Perl VLSI Computer_Architecture Digital_Systems Logic_Synthesis Timing_Analysis
Hybrid
Save

Senior ASIC Design Engineer – Clocks IP

Nvidia

Santa Clara, CA 16 days ago $136,000–$218,500
Verilog Python RTL Logic Synthesis CI/CD Sub-micron Silicon Issues Clocking Networks Clocks Controller Power Optimization Noise Analysis Cross-talk OCV Effects Scalable Designs Silicon Debug
Hybrid
Save