FE Design and Timing Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $126,800–$220,900 / yr
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $176k

This role $174k

$116k most similar roles pay here $232k

This role pays more than 55% of similar roles. Most pay $142,400–$209,750 — the shaded band above. At the midpoint, this role pays about $174k versus about $176k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · FE Design and Timing Engineer

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As a FE Design and Timing Engineer at Apple, you will join a small, dedicated team responsible for transforming RTL into final GDSII for high-performance, low-power wireless SoCs. Your daily tasks include generating static timing constraints, synthesizing designs with UPF/DFT/BIST, closing timing on critical blocks, and optimizing performance through functional ECOs. You will collaborate closely with RTL designers, CAD teams, and physical design engineers to ensure timely delivery of top-quality products. Essential skills for this role include expertise in ASIC design flow, synthesis, static timing analysis, and scripting languages like TCL, Perl, or Python. Additionally, knowledge of SoC architecture, Verilog/SystemVerilog, and low-power design techniques is crucial. This highly visible position offers a critical impact on the development of leading-edge products that delight millions of customers worldwide.

Skills

TCL Perl Python Verilog SystemVerilog Timing_Corner_Analysis UPF DFT BIST Static_Timing_Analysis Place_and_Route Floor_Planning CTS Routing Signal_Integrity Logic_Equivalence_Checking Physical_Design Synthesis ASIC_Design_Flow

What you'll do

Generate chip or block level static timing constraints.
Close timing on critical blocks by working with design and PD teams.
Perform timing optimization and implement the design for functionality.
Run static timing analysis flows at chip/block level and provide guidelines to fix violations.
Participate in establishing/improving CAD and design flow methodologies.

What we're looking for

Experience in generating chip or block level static timing constraints.
Proficiency in scripting languages such as TCL, Perl, or Python.
Knowledge of ASIC design flow, synthesis, and static timing analysis.
Hands-on experience with industry-standard Timing and Physical Design tools.
Understanding of UPF and low-power design implementation techniques.
Familiarity with DFT methodologies including Scan and BIST.
Experience in collaborating with logic design teams for timing fixes.

Similar roles

FE Design and Timing Engineer

Apple Inc

San Diego, CA 52 days ago $120,300–$210,100

TCL Perl Python Verilog SystemVerilog UPF DFT BIST Static_Timing_Analysis Logic_Equivalence Physical_Design Synthesis SDC Place_and_Route Floor_Planning CTS Routing Signal_Integrity Low_Power_Design

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