Timing Design Engineer

Apple Inc

Confirmed live 2 days ago Low trust

Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$129,300–$225,300 / yr
Posted
143 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $187k
This role $177k
$118k most similar roles pay here $237k

This role pays more than 50% of similar roles. Most pay $159,525–$214,000 — the shaded band above. At the midpoint, this role pays about $177k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Timing Design Engineer

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As a Timing Design Engineer, you will join the hardware team as an ASIC STA Engineer responsible for all aspects of SoC design regarding timing. Your daily responsibilities include performing timing sign-off, developing STA and sign-off flows, and managing IP and block level timing constraints from synthesis through to final sign-off. You will collaborate with RTL designers to understand design intent and clock structures, work with CAD teams to develop flows, and partner with physical design teams to achieve quality timing closure. The role requires expertise in Primetime tools, SDC constraint generation, and managing timing corners, modes, process variations, and signal integrity issues. You must be proficient in Tcl and Perl scripting while possessing knowledge of synthesis, DFT, and backend methodologies to resolve potential pessimism or fallouts in complex timing analysis for integrated circuits.

Skills

STA Primetime SDC Tcl Perl ASIC Design Timing Closure Synthesis DFT Backend RTL Signal Integrity SoC Design

What you'll do

  • Perform timing sign-off and manage all aspects of SoC design timing.
  • Develop STA and sign-off flows to ensure high-quality timing results.
  • Own IP and block level timing constraints from synthesis through to final sign-off.
  • Collaborate with RTL designers to understand design intent and clock structures.
  • Work with CAD teams to develop and improve timing analysis flows.
  • Coordinate with the Physical Design team to achieve successful timing closure.
  • Create plans and methods to verify internal timing constraints.
  • Innovate timing constraints and flow to reduce pessimism and prevent fallouts in analysis.

What we're looking for

  • Bachelor of Science in Electrical Engineering.
  • Proven knowledge of ASIC design timing closure flow and methodology.
  • 2+ years of experience in writing ASIC timing constraints and timing closure.
  • Expertise in STA tools (Primetime) and flow, including timing corners, modes, process variations, and signal integrity.
  • Hands-on experience in timing/SDC constraints generation and management.
  • Proficiency in scripting languages such as Tcl and Perl.
  • Familiarity with synthesis, DFT, and backend related methodology and tools.
  • Strong communication skills for collaborating with diverse teams.

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