Timing Design Engineer
Quick summary
- Work type
- On-site
- Location
- Cupertino, CA
- Salary
- $126,800–$220,900 / yr
- Posted
- 45 days ago
Market check
Salary context
Competitive pay
How this pay compares to similar roles
Similar $181k
This role $174k
$116k
most similar roles pay here
$232k
This role pays less than 59% of similar roles. Most pay $152,875–$209,750 — the shaded band above. At the midpoint, this role pays about $174k versus about $181k for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has 638 open roles on FindRole.
Listed pay typically runs $171,600–$272,100 across 505 roles with salary data.
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At a glance
TL;DR · Timing Design Engineer
As a Timing Design Engineer at our leading-edge semiconductor company, you will join the high-performance computing team as a mid-level professional. Your primary responsibilities include designing and optimizing timing closure for complex digital circuits, ensuring robust performance across various process nodes. You will work closely with layout designers to implement detailed timing analysis and develop innovative solutions to meet stringent design requirements. The role demands expertise in industry-standard tools like Cadence Genus and Synopsys IC Compiler II, along with a strong foundation in Verilog or SystemVerilog for simulation purposes. Additionally, you should possess deep knowledge of static timing analysis techniques and be adept at scripting languages such as Python or Perl to automate tasks. This position offers an opportunity to tackle cutting-edge challenges in high-speed interconnects and low-power design methodologies within a fast-paced environment.
What you'll do
- Analyze and optimize system timing to ensure reliable operation.
- Develop timing constraints for design implementation and verification.
- Perform static timing analysis to identify potential timing violations.
- Collaborate on the creation of timing simulation models and testbenches.
- Document timing issues and their resolutions thoroughly for future reference.
What we're looking for
- Bachelor’s degree in Electrical Engineering or related field required.
- Proven experience in timing analysis and optimization for high-speed digital circuits.
- Strong understanding of clock distribution networks and phase-locked loops (PLLs).
- Experience with industry-standard EDA tools for timing closure and simulation.
- Knowledge of signal integrity, power integrity, and thermal management techniques.
- Familiarity with IEEE standards relevant to digital circuit design and verification.
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