FE Design and Timing Engineer

Apple Inc

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $120,300–$210,100 / yr
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $176k

This role $165k

$110k most similar roles pay here $221k

This role pays less than 58% of similar roles. Most pay $142,400–$209,750 — the shaded band above. At the midpoint, this role pays about $165k versus about $176k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · FE Design and Timing Engineer

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As a FE Design and Timing Engineer at Apple, you will join a small, dedicated team responsible for transforming RTL into final GDSII for high-performance, low-power wireless SoCs. Your day-to-day responsibilities include generating static timing constraints, synthesizing designs with UPF/DFT/BIST, closing timing on critical blocks, and performing optimization to ensure functionality. You will collaborate closely with RTL designers, CAD teams, and physical design engineers to meet stringent power, performance, and area goals. Key skills required are expertise in ASIC design flow, synthesis, static timing analysis, and scripting languages like TCL, Perl, or Python. Familiarity with industry-standard tools for Timing, Logic Equivalence, Physical Design, and Synthesis is essential, along with knowledge of SoC architecture and HDL languages such as Verilog/SystemVerilog. This role demands a deep understanding of low-power design techniques, DFT methodologies, and place-and-route steps to ensure designs are delivered on time and meet the highest quality standards for Apple’s cutting-edge products.

Skills

TCL Perl Python Verilog SystemVerilog UPF DFT BIST Static_Timing_Analysis Logic_Equivalence Physical_Design Synthesis SDC Place_and_Route Floor_Planning CTS Routing Signal_Integrity Low_Power_Design

What you'll do

Generate chip or block level static timing constraints for high performance designs.
Close timing on critical blocks by collaborating with design and physical design teams.
Perform timing optimization and implement functional ECOs to enhance design quality.
Run static timing analysis flows at the chip/block level, providing guidelines to fix violations.
Participate in establishing and improving CAD methodologies and design flow processes.

What we're looking for

Experience in generating chip or block level static timing constraints.
Proficiency in scripting languages such as TCL, Perl, or Python.
Knowledge of ASIC design flow, synthesis, and static timing analysis.
Hands-on experience with industry-standard Timing and Physical Design tools.
Understanding of UPF and low-power design implementation techniques.
Familiarity with DFT methodologies including Scan and BIST.
Experience in closing timing on critical blocks by collaborating with teams.

Similar roles

FE Design and Timing Engineer

Apple Inc

Sunnyvale, CA 52 days ago $126,800–$220,900

TCL Perl Python Verilog SystemVerilog Timing_Corner_Analysis UPF DFT BIST Static_Timing_Analysis Place_and_Route Floor_Planning CTS Routing Signal_Integrity Logic_Equivalence_Checking Physical_Design Synthesis ASIC_Design_Flow

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