Timing Design Engineer
Quick summary
- Work type
- On-site
- Location
- Melbourne, FL
- Posted
- 45 days ago
Market check
Salary context
How this pay compares to similar roles
Similar $181k
$126k
most similar roles pay here
$228k
This listing doesn't post a salary. Most similar roles pay $152,875–$209,750.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has 638 open roles on FindRole.
Listed pay typically runs $171,600–$272,100 across 505 roles with salary data.
Most-posted roles
- Analog Layout Engineer 8
- GPU Performance Engineer, Platform Architecture 8
- Touch HW EE Validation Engineer 6
- ASIC Design Engineer - Pixel IP DMA 5
- Software Development Engineer 5
At a glance
TL;DR · Timing Design Engineer
As a Timing Design Engineer at our leading-edge hardware company in Melbourne, Florida, you will join the high-performance computing team as a mid-level professional. Your primary responsibilities include designing and optimizing timing closure for complex digital circuits to ensure reliable operation within strict performance constraints. Day-to-day tasks involve collaborating with cross-functional teams to analyze design issues, develop innovative solutions, and implement robust verification methodologies. You should be proficient in industry-standard EDA tools such as Synopsys and Cadence, have a strong grasp of Verilog or SystemVerilog, and possess expertise in timing analysis and optimization techniques. This role requires an understanding of high-speed digital circuits and the ability to work on cutting-edge technology that addresses critical challenges in semiconductor design at scale.
What you'll do
- Develop and optimize timing constraints for complex digital circuits.
- Analyze post-layout simulation results to identify and resolve timing issues.
- Collaborate on the creation of test benches for verifying timing requirements.
- Implement strategies to meet timing closure goals in semiconductor designs.
- Document detailed reports on timing analysis and optimization processes.
What we're looking for
- Bachelor’s degree in Electrical Engineering or related field required.
- At least 3 years of experience in semiconductor timing design and analysis.
- Proficient in using EDA tools for simulation and verification.
- Strong understanding of CMOS circuit design principles and techniques.
- Experience with signal integrity analysis and mitigation strategies.
More like this
Similar roles
Timing Design Engineer
Apple Inc
San Diego, CA
45 days ago
$120,300–$210,100
Verilog
SystemC
VHDL
Cadence
Synopsys
Tensilica
Mentor Graphics
ModelSim
Python
Git
JIRA
Confluence
CI/CD
Physical Design Timing Engineer (STA)
Broadcom
San Jose, CA
15 days ago
$141,300–$226,000
Tcl
Python
Perl
Cadence
Synopsys
ASIC
STA
SDC
On-Chip_Variation
Signal_Integrity
IR-drop_aware_STA
MMMC_Analysis
ECOs
RTL
Physical_Design
DFT
Power_Performance_Area_Tradeoffs
EDA_Tools
Senior ASIC Timing Engineer
Nvidia
Santa Clara, CA
3 days ago
$136,000–$218,500
Static Timing Analysis
Timing Constraints Generation
ECOs
Physical Design Optimization
Synthesis
Placement
Routing
Logic Restructuring
STA Tools
Deep Sub-Micron Process Nodes
GPU STA
CPU STA
LPD STA
SOC STA
Logic Synthesis
Equivalence Checking
DFT Logic
AMS Designs
Methodology Development
Flow Development
Automation
Hybrid