Timing Design Engineer

Apple Inc

Confirmed live yesterday Low trust

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Work type
On-site
Location
Austin, TX
Posted
143 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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Similar $187k
$133k most similar roles pay here $228k

This listing doesn't post a salary. Most similar roles pay $159,700–$214,000.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Timing Design Engineer

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As a Timing Design Engineer, you will join the hardware team as an ASIC STA Engineer responsible for all aspects of SoC design regarding timing. Your daily responsibilities include performing timing sign-off, developing STA and sign-off flows, and managing IP and block level timing constraints from synthesis through to final sign-off. You will collaborate with RTL designers to understand clock structures, work with CAD teams to develop tools, and partner with physical design teams to achieve quality timing closure. The role requires expertise in Primetime, SDC constraint generation, and scripting languages like Tcl and Perl. You must address technical challenges involving timing corners, modes, process variations, and signal integrity issues. This position focuses on solving complex timing analysis problems by innovating constraints and flows to eliminate pessimism and ensure robust performance for integrated circuits.

Skills

STA Primetime SDC Tcl Perl ASIC Design Timing Closure Synthesis DFT RTL Signal Integrity SoC Design Physical Design

What you'll do

  • Perform timing sign-off and develop STA and sign-off flows for SoC designs.
  • Manage IP and block level timing constraints from synthesis through final sign-off.
  • Collaborate with RTL designers to analyze design intent and clock structures.
  • Work with CAD teams to develop and optimize timing analysis flows.
  • Coordinate with Physical Design teams to achieve and close timing requirements.
  • Develop plans and methods to verify internal timing constraints.
  • Innovate timing constraints and flow to eliminate pessimism or fallouts in analysis.

What we're looking for

  • Bachelor of Science in Electrical Engineering.
  • Proven knowledge of the ASIC design timing closure flow and methodology.
  • 2+ years of experience in writing ASIC timing constraints and timing closure.
  • Expertise in STA tools (Primetime) and flow, including timing corners, modes, process variations, and signal integrity.
  • Hands-on experience in timing/SDC constraints generation and management.
  • Proficiency in scripting languages such as Tcl and Perl.
  • Familiarity with synthesis, DFT, and backend related methodology and tools.
  • Strong communication skills for collaborating with diverse teams.

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