Timing Design Engineer

Apple Inc

Quick summary

Work type
On-site
Location
Waltham, MA
Salary
$114,100–$199,000 / yr
Posted
45 days ago

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $181k
This role $157k
$102k most similar roles pay here $231k

This role pays less than 70% of similar roles. Most pay $152,875–$209,750 — the shaded band above. At the midpoint, this role pays about $157k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 638 open roles on FindRole.

Listed pay typically runs $171,600–$272,100 across 505 roles with salary data.

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At a glance

TL;DR · Timing Design Engineer

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As a Timing Design Engineer at our leading-edge semiconductor company, you will join the high-performance computing team as a mid-level professional. Your primary responsibilities include designing and optimizing timing closure for complex digital circuits to ensure reliable chip performance. You will work closely with design engineers to analyze and resolve timing issues, develop scripts for automated timing analysis, and collaborate on advanced clocking schemes to enhance system efficiency. The ideal candidate should have expertise in Cadence Genus or Synopsys IC Compiler II, TCL scripting, and a solid understanding of digital logic design principles. Experience with large-scale SoC projects is highly valued as you will be tackling intricate challenges related to high-speed interconnects and multi-core processor architectures.

What you'll do

  • Develop and optimize timing constraints for complex digital circuits.
  • Analyze and resolve timing violations in circuit designs using industry tools.
  • Collaborate on the creation of test benches to validate timing requirements.
  • Conduct static timing analysis to ensure design meets performance targets.
  • Document timing-related issues and propose corrective actions or workarounds.

What we're looking for

  • Bachelor’s degree in Electrical Engineering or related field required.
  • Proven experience in timing analysis and optimization for high-speed digital designs.
  • Strong understanding of clock distribution networks and phase-locked loops (PLLs).
  • Experience with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics.
  • Knowledge of IEEE standards including 802.3 Ethernet and USB protocols preferred.
  • Excellent problem-solving skills and ability to work in a fast-paced environment.
  • Familiarity with scripting languages like Python for automation tasks beneficial.

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