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Active Keyword: Sr. Silicon Design Engineer Remove filter Clear all

13 of up to 20 (filtered)

Senior Silicon Design Engineer

Amd

Santa Clara, CA 2 days ago $141,760–$212,640
Actively hiring Confirmed live yesterday Posted this week High trust Below market
Physical Design AI Automation Python LLM Digital Design Verification Data Analysis Mathematical Modeling Scripting Processor Architecture
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Senior ASIC Design Engineer, Silicon Engineering

SpaceX

Irvine, CA +3 8 days ago $165,000–$265,000
Actively hiring Confirmed live today High trust Competitive pay
RTL Verilog System Verilog ASIC SoC AXI AHB Python EDA Tools HDL Simulators Timing Closure Synthesis Clock Domain Crossing Power Optimization Silicon Bring-up
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Senior ASIC Design Engineer, Silicon Engineering

SpaceX

Redmond, WA +3 8 days ago $165,000–$270,000
Actively hiring Confirmed live today High trust Above market
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB EDA Tools HDL Simulators Timing Closure Synthesis Clock Domain Crossing Power Optimization Silicon Bring-up
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Senior ASIC Design Engineer, Silicon Engineering

SpaceX

Austin, TX +3 8 days ago
Actively hiring Confirmed live today Trusted
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB Synthesis Timing Closure HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization
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Senior Manager Silicon Design Engineering

Amd

Austin, TX +2 50 days ago $186,400–$279,600
Actively hiring Confirmed live yesterday High trust Above market
UVM System Verilog C-DPI FPGA ASIC Firmware SoC AXI AHB DMA Cryptography Data Compression Silicon Bring-up Emulation Micro-architecture
Hybrid
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Senior ASIC Design Verification Engineer

SpaceX

Austin, TX 86 days ago
Actively hiring Confirmed live today Low trust
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design
5+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Redmond, WA 86 days ago $165,000–$260,000
Actively hiring Confirmed live today Low trust Competitive pay
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design
5+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Palo Alto, CA 86 days ago $175,000–$280,000
Actively hiring Confirmed live today Low trust Above market
ASIC UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Test Bench Development Object-Oriented Programming Digital Design
5+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Irvine, CA 86 days ago $165,000–$260,000
Actively hiring Confirmed live yesterday Low trust Competitive pay
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification test bench development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Scripting Functional Coverage
5+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Irvine, CA +2 135 days ago $165,000–$260,000
Actively hiring Confirmed live today Low trust Competitive pay
ASIC SOC Physical Design RTL2GDSII Static Timing Analysis (STA) EDA Tools Python TCL Perl Bash Makefile DFT Scan MBIST LBIST FinFET CMOS Floorplanning Place and Route Synthesis
5+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Palo Alto, CA +3 135 days ago $175,000–$280,000
Actively hiring Confirmed live today Low trust Above market
ASIC Physical Design RTL2GDSII STA EDA Tools Python TCL Perl Bash Makefile DFT Scan MBIST LBIST FinFET CMOS Floorplanning Place and Route Synthesis Electromigration
5+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Austin, TX +2 135 days ago
Actively hiring Confirmed live today Low trust
ASIC SOC Physical Design RTL2GDSII Static Timing Analysis STA Floorplanning Place and Route DFT Scan MBIST LBIST FinFET CMOS Python TCL Perl Bash Makefile EDA Tools
5+ yrs exp
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