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Verilog SystemVerilog UVM Python Perl Veloce Palladium Zebu HAPS PCIe Ethernet RDMA TCP Fiber Channel Formal verification iEV/vc formal Jasper Gold AI agents Cursor Codex CoPilot Forwarding logic Parsers P4 +19 more Show less

Python CI/CD

Python CI/CD

Python CI/CD

Python CI/CD

Python ASIC verification FPGA verification

Python CI/CD

Python ASIC verification FPGA verification

Python CI/CD

UVM Python

UVM Python

UVM Python

UVM Python

UVM C Verilog SystemVerilog Python Docker CI/CD Kubernetes AWS Azure PostgreSQL Git Jira Prometheus Grafana +10 more Show less

UVM SystemVerilog Verilog PCIe NVMe RDMA Python CI/CD Kubernetes AWS GitHub JIRA PostgreSQL Mentor Graphics Questa Simulator Cadence Incisive Verilog Simulator +10 more Show less

SystemVerilog UVM Python C++ Verilog SystemC TLM Simulation tools Distributed compute environment HLS tools CI/CD +6 more Show less

SystemVerilog UVM VMM OVM Synopsys VCS Cadence IES AXI3/4 DDR4/5 HBM PCIe ASIC FPGA SOC NetWork on Chip (NOC) verification gate level simulation power verification reset verification contention checking abstraction techniques formal property checking tools Cadence IEV Jasper Synopsys VC-Formal Synopsys Magellan +19 more Show less