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Active Keyword: Silicon Design Verification Engineer Remove filter Clear all

15 of up to 20 (filtered)

Silicon Design Verification Engineer

Microsoft

2 days ago $102,100–$202,200
Actively hiring Confirmed live yesterday Posted this week High trust Below market
C C++ Python SystemVerilog FPGA Xilinx HAPS JTAG Logic Analyzers Oscilloscopes SoC Firmware Assembly AMBA AXI AHB APB SPI I2C I3C USB
2+ yrs exp Hybrid
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Principal Silicon Design Verification Engineer

Microsoft

7 days ago $142,800–$274,800
Actively hiring Confirmed live yesterday Posted this week Trusted Competitive pay
PCIe UVM System Verilog Verilog NVMe RDMA SoC Digital Design Computer Architecture Verification IP Tapeout Data Link Layer
8+ yrs exp Hybrid
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Senior Silicon Design Verification Engineer

Amd

Austin, TX 8 days ago $144,800–$217,200
Actively hiring Confirmed live yesterday High trust Competitive pay
UVM SystemVerilog Verilog C++ C SystemC TLM RTL Linux Windows Perl Ruby Shell Scripting Makefiles HLS ASIC Verification Simulation Firmware Graphics Pipeline
Hybrid
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Design Verification Engineer, Silicon Engineering

SpaceX

Palo Alto, CA 80 days ago $135,000–$155,000
Actively hiring Confirmed live yesterday Low trust Below market
ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Chip Bring-up
1+ yrs exp
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Design Verification Engineer, Silicon Engineering

SpaceX

Austin, TX 80 days ago
Actively hiring Confirmed live yesterday Low trust
ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Chip Bring-up Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Scripting
1+ yrs exp
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Design Verification Engineer, Silicon Engineering

SpaceX

Irvine, CA 80 days ago $125,000–$145,000
Actively hiring Confirmed live yesterday Low trust Below market
ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Chip Bring-up
1+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Austin, TX 80 days ago
Actively hiring Confirmed live yesterday Low trust
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design
5+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Redmond, WA 80 days ago $165,000–$260,000
Actively hiring Confirmed live yesterday Low trust Competitive pay
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design
5+ yrs exp
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Design Verification Engineer, Silicon Engineering

SpaceX

Redmond, WA 80 days ago $125,000–$145,000
Actively hiring Confirmed live yesterday Low trust Below market
ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Chip Bring-up
1+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Palo Alto, CA 80 days ago $175,000–$280,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Test Bench Development Object-Oriented Programming Digital Design
5+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Irvine, CA 80 days ago $165,000–$260,000
Actively hiring Confirmed live yesterday Low trust Competitive pay
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification test bench development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Scripting Functional Coverage
5+ yrs exp
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Principal Design Verification Engineer

SpaceX

Palo Alto, CA 134 days ago $210,000–$355,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp
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Principal Design Verification Engineer

SpaceX

Irvine, CA 134 days ago $210,000–$335,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp
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Principal Design Verification Engineer

SpaceX

Redmond, WA 134 days ago $210,000–$335,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp
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Principal Design Verification Engineer

SpaceX

Austin, TX 134 days ago
Actively hiring Confirmed live yesterday Low trust
ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp
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