Principal Silicon Design Verification Engineer | Microsoft Careers

Microsoft

Quick summary

Work type
On-site
Location
Salary
$142,800–$274,800 / yr
Posted
2 days ago
Closes
Nov 30, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k
This role $209k
$127k most similar roles pay here $291k

This role pays more than 71% of similar roles. Most pay $171,125–$216,250 — the shaded band above. At the midpoint, this role pays about $209k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 728 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 664 roles with salary data.

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At a glance

TL;DR · Principal Silicon Design Verification Engineer | Microsoft Careers

As a Principal Engineer in the Data Processing Unit team, you will validate silicon to solve complex datacenter problems by leading key components of functional validation for complex ASIC SOC using UVM/C test benches. You will collaborate with architecture, design, verification, and partner teams to define testing strategies, develop comprehensive test plans, and create C tests and infrastructure for functional validation. Your responsibilities include debugging failures, creating stress and performance scenarios, participating in chip bring-up, and writing test firmware to support various teams. Additionally, you will innovate to improve validation efficiency through methodologies and tools while coaching and mentoring others in your areas of expertise. This role requires extensive experience in pre-silicon validation with a focus on high-performance network switches/accelerators, CPUs, vector processors, and GPUs, along with proficiency in Verilog, SystemVerilog, UVM-based testbenches, and knowledge of Ethernet, TCP/IP, ROCEv2, MAC/PCS, and networking NIC/Switches.

What you'll do

  • Lead the functional validation of complex ASIC SOC using UVM/C test bench.
  • Define testing strategies for pre-silicon SoC verification and post-silicon validation.
  • Develop comprehensive test plans and C tests to validate complex design functionality.
  • Debug failures, create stress scenarios, and optimize performance during chip bring-up.
  • Innovate methodologies and tools to enhance validation efficiency and project outcomes.

What we're looking for

  • 10+ years of experience in pre-silicon validation for high-performance network switches/accelerators.
  • Proven expertise in UVM/C verification methodology and complex SoC development.
  • Deep knowledge of Ethernet, TCP/IP, ROCEv2, MAC/PCS, and networking NIC/Switches.
  • Strong proficiency in Verilog, SystemVerilog, and UVM-based testbench environment.
  • Experience in building UVM testbenches and managing regressions for successful tapeout.

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