Principal Silicon Design Verification Engineer | Microsoft Careers

Microsoft

Quick summary

Work type: On-site
Location: US
Salary: $142,800–$274,800 / yr
Posted: 2 days ago
Closes: Nov 30, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k

This role $209k

$127k most similar roles pay here $291k

This role pays more than 71% of similar roles. Most pay $171,125–$216,250 — the shaded band above. At the midpoint, this role pays about $209k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 728 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 664 roles with salary data.

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At a glance

TL;DR · Principal Silicon Design Verification Engineer | Microsoft Careers

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Senior Verification Engineer position available on the PCIe IP team, focusing on functional validation at block, cluster, or fullchip levels using UVM/C test bench and Verification IP. Responsibilities include developing comprehensive test plans, writing unit tests, managing regression suites, debugging failures, and driving timely resolution to improve validation efficiency through innovative methodologies and tools. Ideal candidates possess experience with PCIe protocol verification, particularly Gen6/Gen7 standards like NVMe or RDMA, and have a strong background in Verilog, System Verilog, and UVM-based testbench environments. A deep understanding of computer architecture and digital design fundamentals is essential, along with proven success in building UVM testbenches and meeting code coverage goals for successful tapeout.

Skills

UVM SystemVerilog Verilog PCIe NVMe RDMA Python CI/CD Kubernetes AWS GitHub JIRA PostgreSQL Mentor Graphics Questa Simulator Cadence Incisive Verilog Simulator

What you'll do

Conduct functional validation of PCIe IP at various levels using UVM/C test bench.
Develop comprehensive test plans and unit tests for thorough verification.
Manage regression suites, troubleshoot issues, and ensure timely resolution.
Enhance validation efficiency by innovating methodologies and tools.
Achieve code coverage and functional coverage goals for successful tapeout.

What we're looking for

Extensive experience in PCIe protocol verification, including Gen6/Gen7 standards.
Proficiency in Verilog, System Verilog, and UVM-based testbench environment.
Experience with cluster, SoC, or fullchip level verification for PCIe IP.
Strong understanding of computer architecture and digital design fundamentals.
Ability to develop and manage regression suites, achieving code and functional coverage goals.

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