Silicon Design Verification Engineer in Austin, Texas | Advanced Micro Devices, Inc

Amd

Quick summary

Work type
On-site
Location
Santa Clara, CASan Diego, CAAustin, TXLongmont, CO
Salary
$121,680–$121,680 / yr
Posted
98 days ago
Closes
Mar 6, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $187k
This role $122k
$110k most similar roles pay here $230k

This role pays less than 98% of similar roles. Most pay $162,700–$212,000 — the shaded band above. At the midpoint, this role pays about $122k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 71 open roles on FindRole.

Listed pay typically runs $178,400–$178,400 across 71 roles with salary data.

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At a glance

TL;DR · Silicon Design Verification Engineer in Austin, Texas | Advanced Micro Devices, Inc

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Join our dynamic Verification Engineering team as a Design Verification Engineer and contribute to AMD's mission of delivering cutting-edge technologies. You will plan verification for complex digital design blocks by collaborating with architects and designers to create comprehensive test plans, design System Verilog and UVM-based testbenches, and debug tests to ensure functional correctness. Utilize advanced tools like Synopsys VCS and Cadence IES for simulation, and enhance coverage measures to identify verification gaps. Ideal candidates have experience in developing UVM, OVM, and VMM test benches, formal property checking with tools such as Jasper and VC-Formal, and a strong grasp of ASIC development phases. Knowledge in protocols like AXI3/4, DDR4/5, HBM, PCIe, processors, and graphics is beneficial.

Skills

SystemVerilog UVM VMM OVM Synopsys VCS Cadence IES AXI3/4 DDR4/5 HBM PCIe ASIC FPGA SOC NetWork on Chip (NOC) verification gate level simulation power verification reset verification contention checking abstraction techniques formal property checking tools Cadence IEV Jasper Synopsys VC-Formal Synopsys Magellan

What you'll do

  • Plan verification for complex digital design blocks by understanding architecture and specifications.
  • Design testbenches in System Verilog and UVM to efficiently verify designs.
  • Create and enhance constrained-random and directed verification environments using SVA.
  • Debug tests with design engineers to ensure functionally correct design blocks.
  • Perform coverage analysis to identify verification gaps and achieve closure on metrics.

What we're looking for

  • Experience with System Verilog and UVM for testbench design.
  • Strong understanding of verification techniques including assertion-driven methods.
  • Background in ASIC or full custom chip development phases.
  • Proficiency in using simulation tools like Synopsys VCS, Cadence IES.
  • Ability to create comprehensive verification plans and testbenches.
  • Familiarity with formal property checking tools such as Jasper and Synopsys VC-Formal.
  • Bachelors or Masters degree in Computer Engineering/Electrical Engineering.

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