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Physical Design GDSII Floorplanning PnR Timing Closure IR/EM Analysis Tcl Perl Python Low-power IC Design Physical Verification +6 more Show less

Verilog VHDL RTL ASIC STA CDC Lint Synthesis Python Perl C Unix High-Level Synthesis DSP Ethernet OTN Silicon Debugging Design for Test Design for Manufacturing +14 more Show less

RTL Design Silicon Technology Ethernet IP Switching Python Perl Si Debug front end design AI/ML Data Centers +5 more Show less

SystemVerilog UVM Verilog C++ C ASIC Verification FPGA Ethernet PCIe Routing Switching Object-Oriented Programming Simulation Tape-out +9 more Show less

ASIC Verilog Synthesis Timing Analysis TCL Perl Synopsys Design Compiler Cadence RTL Compiler Primetime Liberty LIB Formal Verification Synopsys Formality Cadence Conformal Spyglass Lint DFT Scan Methodology Git SVN +13 more Show less

C++ VLSI Physical Design EDA Tools Machine Learning Graph Neural Networks Python Tcl Perl multithreading Distributed Computing ICC2 Innovus PrimeTime Tempus StarRC +10 more Show less

C++ VLSI Physical Design Machine Learning Graph Neural Networks Python Tcl Perl ICC2 Innovus PrimeTime Tempus StarRC Multithreading Distributed Computing Parallel Computing EDA Tools +12 more Show less

ASIC Verilog Synthesis Timing Analysis TCL Perl Synopsys Design Compiler Cadence RTL Compiler Primetime Formal Verification Synopsys Formality Cadence Conformal Spyglass Lint DFT Scan Methodology Git SVN +12 more Show less

C++ VLSI Physical Design Computational Geometry Graph Theory Machine Learning ICC2 Innovus Multithreading Distributed Computing Algorithm Development C++17 C++14 +7 more Show less

SystemVerilog UVM C RTL ATE Testbenches Networking Switch Design Design Verification +4 more Show less

SystemVerilog UVM C RTL ATE Testbenches Networking Switch Design Design Verification +4 more Show less